Chrontel
CH7025/CH7026
Advance Information
CH7025/CH7026 TV/VGA Encoder
F
EATURES
•
Support multiple output formats. Such as SDTV format
(NTSC and PAL), HDTV format for 480p,576p,720p and
1080i, analog RGB output for VGA. Sync signals can be
provided
in
separated
or
composite
manner
(Programmable composite sync generation).
Three on-chip 10-bit high speed DACs providing flexible
output capabilities. Such as single, double or triple CVBS
outputs, YPbPr output, RGB output and simultaneous
CVBS and S-video outputs.
Internal embedded 16Mbits SDRAM is used as frame
buffer. Supporting for frame rate conversion. 90/180/270
degree image rotation and vertical or horizontal flip
functions are supported.
Programmable
24-bit/18-bit/16-bit/15-bit/12-bit/8-bit
digital input interface supports various RGB (RGB888,
RGB666, RGB565 and etc), YCbCr (4:4:4 YCbCr,
ITU656) and 2x or 3x multiplexed input. CPU/Memory
interface are supported.
Support for flexible input resolution is up to 800x800 and
1024x680. 320x240, 640x480, 960x720 are support.
Bypass mode is supported.
Flexible up and down scaling engine is embedded
including de-flickering capability. Text enhancement is
supported.
Pixel by pixel brightness, contrast, hue and saturation
adjustment for each kind of output are supported. For
RGB output, only brightness and contrast adjustment are
supported.
Pixel by pixel horizontal position adjustment and line by
line vertical position adjustment are supported.
Fully programmable through serial port. IO and SPC/SPD
voltage supported is from 1.2V to 3.3V.
TV/Monitor connection detect capability.
Programmable power management. DAC can be switched
off based on detection result (Driver support is required).
Flexible pixel clock frequency from graphics controller is
supported (2.3MHz –120MHz). Flexible input clock from
crystal or oscillator is supported (2.3MHz – 64MHz).
Macrovision
TM
7.1.L1 for SDTV is supported in CH7025
(CH7026 is Non-Macrovision part.). Macrovision
TM
copy
protection support for progressive scan TV (480p, 576p
CH7025 only).
CGMS-A support for SDTV and HDTV (CH7025 only).
Offered in BGA or QFP package.
G
ENERAL
D
ESCRIPTION
The CH7025/CH7026 is a device targeting handheld
and similar consumer systems which accept digital
input signal. CH7025/CH7026 encodes and transmits
data through 10-bit DACs. The device is able to
encode
the
video
signals
and
generate
synchronization signals SDTV format for NTSC and
PAL
standards
and
HDTV
format
for
480p,576p,720p and 1080i. Analog RGB output and
composite SYNC signal are also supported. The
device accepts different data formats including RGB
and YCbCr (e.g. RGB565, RGB666, RGB888,
ITU656 like YCbCr, etc.).Both interlaced and non-
interlaced input data formats are supported. 16Mbit
SDRAM is embedded in package. Frame rate
conversion, Image rotation, zooming and scaling, are
supported.
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Note: the above feature list is subject to change without notice. Please contact Chrontel for more information
and current updates.
209-1000-003
Rev. 1.22,
02/21/2010
1
CHRONTEL
CH7025/CH7026
SDRAM
RGB/YCbCr
Input
data
format
decoder
MUX
CSC
(YCbCr
to RGB)
Scaler
MUX
CSC
(RGB to
YUV)
CSB
WEB
VSYNC
DIN
CPU
interface
HUE
SAT
BRI
CON
VP
HP
TV
formater
SPC
Serial
port
MUX
SPD
R/Y/CVBS/Y_Svideo
DAC 0
BRI
CON
VP
HP
PLL
G/Pb/CVBS/C-Svideo
DAC 1
B/Pr/CVBS
DAC 2
XI
XO
CSYNC
H,V,DE
SYNC
position
adjust
Composite
sync
generation
VSYNC
HSYNC
Figure 1: CH7025/CH7026 Block Diagram
2
209-1000-003
Rev. 1.22,
02/21/2010
CHRONTEL
Table of Contents
CH7025/CH7026
F
EATURES
................................................................................................................................................. 1
G
ENERAL
D
ESCRIPTION
.......................................................................................................................... 1
1.0
1.1
1.2
P
IN
-
OUT
...................................................................................................................................... 6
Package Diagram .......................................................................................................................................6
Pin Description ..........................................................................................................................................7
2.0
F
UNCTIONAL
D
ESCRIPTION
.................................................................................................... 11
2.1
Input Interface .......................................................................................................................................11
2.1.1
Overview..........................................................................................................................................11
2.1.2
Input Clock and Data Timing Diagram............................................................................................11
2.1.3
Input Data Voltage...........................................................................................................................12
2.1.4
Input Data Format............................................................................................................................12
2.2
Chip Output ...........................................................................................................................................14
2.2.1
TV Output........................................................................................................................................14
2.2.2
VGA Output.....................................................................................................................................15
2.2.3
Video DAC Output ..........................................................................................................................15
2.2.4
DAC Single/Double Termination ....................................................................................................15
2.2.5
Video DAC Connection Detect .......................................................................................................15
2.2.6
Picture Enhancement .......................................................................................................................15
2.2.7
Color Sub-carrier Generation...........................................................................................................15
2.2.8
ITU-R BT.470 Compliance .............................................................................................................16
2.3
Testing Functions and Power Down Mode ..........................................................................................16
2.3.1
Test Pattern Select ...........................................................................................................................16
2.3.2
SDRAM Power Down .....................................................................................................................16
2.4
Serial Port...............................................................................................................................................16
2.4.1
Introduction......................................................................................................................................16
2.4.2
Electrical Characteristics of the Serial Port ........................................................................................17
2.4.3
Transfer Protocol ..............................................................................................................................17
2.4.4
Chrontel Encoder Write Cycle Protocol (R/W* = 0)..........................................................................18
2.4.5
Chrontel Encoder Read Cycle Protocol (R/W* = 1)...........................................................................19
3.0
3.1
3.2
3.3
3.4
3.5
E
LECTRICAL
S
PECIFICATIONS
............................................................................................... 21
Absolute Maximum Ratings ....................................................................................................................21
Recommended Operating Conditions ......................................................................................................21
Electrical Characteristics .........................................................................................................................22
Digital Inputs / Outputs............................................................................................................................22
AC Specifications ....................................................................................................................................23
4.0
5.0
P
ACKAGE
D
IMENSIONS
................................................................................................ 24
R
EVISION
H
ISTORY
...................................................................................................... 26
209-1000-003
Rev. 1.22,
02/21/2010
3
CHRONTEL
CH7025/CH7026
4
209-1000-003
Rev. 1.22,
02/21/2010
CHRONTEL
FIGURES AND TABLES
List of Figures
CH7025/CH7026
Figure 1: CH7025/CH7026 Block Diagram ......................................................................................................2
Figure 2: BGA Package (Top View) .................................................................................................................6
Figure 3: 80 Pin LQFP Package ........................................................................................................................7
Figure 4: Clock and Data Input Timing in 3x Multiplexed Mode ..................................................................11
Figure 5: SDR and DDR Input Data Formats ..................................................................................................11
Figure 6: Horizontal Input Timing...................................................................................................................12
Figure 7: Vertical Input Timing.......................................................................................................................12
Figure 8: CPU/MEMORY Interface Timing ...................................................................................................12
Figure 9: The Connection of the Serial Port Interface .....................................................................................17
Figure 10: Acknowledge Protocol ...................................................................................................................19
Figure 11:Single-step Write Cycles (2 cycles) ................................................................................................19
Figure 12: Auto-Increment Write Cycle ..........................................................................................................19
Figure 13: Single-step Read Cycles (2 cycles) ................................................................................................20
Figure 14:Auto-increment Read Cycles...........................................................................................................20
Figure 15: 80 Pin TFBGA Package .................................................................................................................24
Figure 16: 80 Pin LQFP Package ....................................................................................................................25
List of Tables
Table 1: Pin Name Description (BGA Package) ...............................................................................................7
Table 2: Pin Name Descriptions (LQFP80 Package).........................................................................................9
Table 3: Input Data Format.............................................................................................................................13
Table 4: Supported SDTV Standards...............................................................................................................14
Table 5: Supported EDTV/HDTV Standards ..................................................................................................14
Table 6: Composite Sync Type........................................................................................................................15
Table 7: Video DAC Configurations for CH7025/CH7026 ............................................................................15
Table 8: Test Pattern Selection ........................................................................................................................16
209-1000-003
Rev. 1.22,
02/21/2010
5
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