NT1GT64U8HA0BN (Green)
1GB : 128M x 64
PC2-3200 / PC2-4200 / PC2-5300 Unbuffered DDR2 SO-DIMM
200 pin Unbuffered DDR2 SO-DIMM
Based on 64Mx8 DDR2 SDRAM
Features
• 200-Pin Small Outline Dual In-Line Memory Module (SO-DIMM)
• 128Mx64 Unbuffered DDR2 SO-DIMM based on 64Mx8 DDR2
SDRAM devices.
• Performance:
PC2-3200 PC2-4200 PC2-5300
Speed Sort
DIMM
f
CK
t
CK
f
DQ
Latency
Clock Frequency
Clock Cycle
DQ Burst Frequency
5A
3
200
5
400
37B
4
266
3.75
533
3C
5
333
3
667
MHz
ns
MHz
Unit
• Intended for 200 MHz, 266MHz, and 333MHz applications
• Inputs and outputs are SSTL-18 compatible
• V
DD
= V
DDQ
= 1.8V ± 0.1V
• SDRAMs have 4 internal banks for concurrent operation
• Module has one physical bank
• Differential clock inputs
• Data is read or written on both clock edges
• DRAM DLL aligns DQ and DQS transitions with clock transitions.
• Address and control signals are fully synchronous to positive
clock edge
• Programmable Operation:
- DIMM
Latency: 3, 4, 5
- Burst Type: Sequential or Interleave
- Burst Length: 4, 8
- Operation: Burst Read and Write
• Auto Refresh (CBR) and Self Refresh Modes
• Automatic and controlled precharge commands
• 14/10/2 Addressing
• 7.8
µs
Max. Average Periodic Refresh Interval
• Serial Presence Detect
• Gold contacts
• SDRAMs in 84-ball FBGA Package
• RoHS Compliance
Description
NT1GT64U8HA0BN is unbuffered 200-Pin Double Data Rate 2 (DDR2) Synchronous DRAM Small Outline Dual In-Line Memory Module
(SO-DIMM), organized as two ranks of 128Mx64 high-speed memory array. Modules use sixteen 64Mx8 84-ball FBGA packaged devices.
These DIMMs are manufactured using raw cards developed for broad industry use as reference designs. The use of these common design
files minimizes electrical variation between suppliers. All NANYA DDR2 SDRAM DIMMs provide a high-performance, flexible 8-byte
interface in a 2.66” long space-saving footprint.
The DIMM is intended for use in applications operating up to 200 MHz (266MHz, 333MHz) clock speeds and achieves high-speed data
transfer rates of up to 400 MHz (533MHz, 667MHz). Prior to any access operation, the device
latency and burst/length/operation type
must be programmed into the DIMM by address inputs A0-A13 and I/O inputs BA0 and BA1 using the mode register set cycle.
The DIMM uses serial presence-detect implemented via a serial EEPROM using a standard IIC protocol. The first 128 bytes of serial PD
data are programmed and locked during module assembly. The remaining 128 bytes are available for use by the customer.
Ordering Information
Part Number
NT1GT64U8HA0BN –5A
NT1GT64U8HA0BN –37B
NT1GT64U8HA0BN –3C
Speed
DDR2-400 PC2-3200 200MHz (5ns @ CL = 3)
DDR2-533 PC2-4200 266MHz (3.75ns @ CL = 4)
DDR2-667 PC2-5300 333MHz (3ns @ CL = 5)
128Mx64
1.8V
Gold
Green
Organization
Power
Leads
Note
REV 1.1
11/2005
1
NANYA reserves the right to change products and specifications without notice.
© NANYA TECHNOLOGY CORPORATION
NT1GT64U8HA0BN (Green)
1GB : 128M x 64
PC2-3200 / PC2-4200 / PC2-5300 Unbuffered DDR2 SO-DIMM
Pin Description
CK0,
CKE0, CKE1
Differential Clock Inputs
Clock Enable
Row Address Strobe
Column Address Strobe
Write Enable
,
A0-A12
A0-A9
A10/AP
BA0, BA1
ODT0, ODT1
NC
Chip Selects
Row Address Inputs
Column Address Inputs
Column Address Input/Auto-precharge
SDRAM Bank Address Inputs
Active termination control lines
No Connect
DQ0-DQ63
DQS0-DQS7
-
DM0-DM7
V
DD
V
REF
V
DDSPD
V
SS
SCL
SDA
SA0, SA1
Data input/output
Bidirectional data strobes
Differential data strobes
Input Data Masks
Power (1.8V)
Ref. Voltage for SSTL_18 inputs
Serial EEPROM positive power supply
Ground
Serial Presence Detect Clock Input
Serial Presence Detect Data input/output
Serial Presence Detect Address Inputs
Pinout
Pin
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
DQS1
V
SS
DQ10
DQ11
V
SS
V
SS
DQ16
DQ17
V
SS
DQS0
V
SS
DQ2
DQ3
V
SS
DQ8
DQ9
V
SS
Front
V
REF
V
SS
DQ0
DQ1
V
SS
Pin Back
2
4
6
8
V
SS
DQ4
DQ5
V
SS
Pin Front
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
DQS2
V
SS
DQ18
DQ19
V
SS
DQ24
DQ25
V
SS
DM3
NC
V
SS
DQ26
DQ27
V
SS
CKE0
V
DD
NC
(BA2)
V
DD
A12
A9
A8
V
DD
A5
A3
Pin
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
DQS3
V
SS
DQ30
DQ31
V
SS
CKE1
V
DD
(A15)
(A14)
V
DD
A11
A7
A6
V
DD
A4
Back
DM2
V
SS
DQ22
DQ23
V
SS
DQ28
DQ29
V
SS
Pin
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
DQS4
V
SS
DQ34
DQ35
V
SS
DQ40
DQ41
V
SS
DM5
V
SS
V
DD
ODT1
V
SS
DQ32
DQ33
V
SS
V
DD
Front
A1
V
DD
A10/AP
BA0
Pin
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
DQS5
V
SS
V
DD
ODT0
(A13)
V
DD
NC
V
SS
DQ36
DQ37
V
SS
DM4
V
SS
DQ38
DQ39
V
SS
DQ44
DQ45
V
SS
Back
A0
V
DD
BA1
Pin Front
151 DQ42
153 DQ43
155 V
SS
157 DQ48
159 DQ49
161 V
SS
163 NC
165 V
SS
167
169 DQS6
171 V
SS
173 DQ50
175 DQ51
177 V
SS
179 DQ56
181 DQ57
183 V
SS
185 DM7
187 V
SS
189 DQ58
191 DQ59
193 V
SS
195 SDA
197 SCL
199 V
DDSPD
Pin Back
152 DQ46
154 DQ47
156 V
SS
158 DQ52
160 DQ53
162 V
SS
164 CK1
166
168 V
SS
170 DM6
172 V
SS
174 DQ54
176 DQ55
178 V
SS
180 DQ60
182 DQ61
184 V
SS
186
188 DQS7
190 V
SS
192 DQ62
194 DQ63
196 V
SS
198 SA0
200 SA1
10 DM0
12 V
SS
14 DQ6
16 DQ7
18 V
SS
20 DQ12
22 DQ13
24 V
SS
26 DM1
28 V
SS
30 CK0
32
34 V
SS
36 DQ14
38 DQ15
40 V
SS
42 V
SS
44 DQ20
46 DQ21
48 V
SS
50 NC
100 A2
Note: All pin assignments are consistent for all 8-byte unbuffered versions.
REV 1.1
11/2005
2
NANYA reserves the right to change products and specifications without notice.
© NANYA TECHNOLOGY CORPORATION
NT1GT64U8HA0BN (Green)
1GB : 128M x 64
PC2-3200 / PC2-4200 / PC2-5300 Unbuffered DDR2 SO-DIMM
Input/Output Functional Description
Symbol
CK0 – CK2,
-
Type
(SSTL)
(SSTL)
Polarity
Cross
Point
Active
High
Active
Low
Active
Low
Active
High
-
Function
The system clock inputs. All the DDR2 SDRAM address and control inputs are sampled on
the cross point of the rising edge of CK and falling edge of
Activates the SDRAM CK signal when high and deactivates the CK signal when low. By
deactivating the clocks, CKE low initiates the Power Down mode, or the Self Refresh
mode.
Enables the associated SDRAM command decoder when low and disables the command
decoder when high. When the command decoder is disabled, new commands are ignored
but previous operations continue.
When sampled at the positive rising edge of the clock,
to be executed by the SDRAM.
Reference voltage for SSTL-18 inputs
On-Die Termination control signals
Selects which SDRAM bank is to be active.
During a Bank Activate command cycle, A0-A13 defines the row address when sampled at
the rising clock edge.
During a Read or Write command cycle, A0-A9, A11 – A13 defines the column address
when sampled at the rising clock edge. In addition to the column address, A10/AP is used
to invoke Autoprecharge operation at the end of the Burst Read or Write cycle. If AP is
high, autoprecharge is selected and BA0/BA1 define the bank to be precharged. If AP is
low, autoprecharge is disabled.
During a Precharge command cycle, AP is used in conjunction with BA0/BA1 to control
which bank(s) to precharge. If AP is high all 4 banks will be precharged regardless of the
state of BA0/BA1. If AP is low, then BA0/BA1 are used to define which bank to pre-charge.
Data and Check Bit Input/Output pins. Check bits are only applicable on the x64 DIMM
configurations.
Power and ground for the DDR2 SDRAM input buffers and core logic
Negative
and
Data strobe for input and output data
Positive
Edge
Active
High
-
-
-
Supply
The data write masks, associated with one data byte. In Write mode, DM operates as a
byte mask by allowing input data to be written if it is low but blocks the write operation if it
is high. In Read mode, DM lines have no effect. DM8 is associated with check bits
CB0-CB7, and is not used on x64 modules.
Address inputs. Connected to either V
DD
or V
SS
on the system board to configure the
Serial Presence Detect EEPROM address.
This bi-directional pin is used to transfer data into or out of the SPD EEPROM. A resistor
must be connected from the SDA bus line to V
DD
to act as a pull-up.
This signal is used to clock data into and out of the SPD EEPROM. A resistor may be
connected from the SCL bus time to V
DD
to act as a pull-up.
Serial EEPROM positive power supply.
CKE0, CKE1
,
(SSTL)
,
V
REF
,
(SSTL)
Supply
Input
(SSTL)
,
,
define the operation
ODT0, ODT1
BA0, BA1
A0 - A9
A10/AP
A11 - A13
(SSTL)
-
DQ0 – DQ63
CB0 – CB7
V
DD
,
V
SS
DQS0 – DQS7
–
(SSTL)
Supply
(SSTL)
Active
High
DM0 – DM7
Input
SA0 – SA2
SDA
SCL
V
DDSPD
REV 1.1
11/2005
3
NANYA reserves the right to change products and specifications without notice.
© NANYA TECHNOLOGY CORPORATION
NT1GT64U8HA0BN (Green)
1GB : 128M x 64
PC2-3200 / PC2-4200 / PC2-5300 Unbuffered DDR2 SO-DIMM
Functional Block Diagram
(1GB, 2Ranks, 64Mx8 DDR2 SDRAMs)
DQS0
DM0
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQS1
DM1
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQS2
DM2
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQS3
DM3
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS
DQS4
DM4
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQS5
DM5
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQS6
DM6
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQS7
DM7
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS
D0
D8
D4
D12
D1
D9
D5
D13
D2
D10
D6
D14
D3
D11
D7
D15
BA0-BA1
A0-A13
CKE0
CKE1
ODT0
ODT1
BA0-BA1 : SDRAMs D0-D17
A0-A13 : SDRAMs D0-D17
: SDRAMs D0-D17
: SDRAMs D0-D17
: SDRAMs D0-D17
CKE : SDRAMs D0-D8
CKE : SDRAMs D9-D17
ODT : SDRAMs D0-D8
ODT : SDRAMs D9-D17
V
DDSPD
V
DDQ
V
DD
V
REF
V
SS
V
DDID
Serial PD
D0-D8
D0-D8
D0-D8
D0-D8
Strap : see Note 4
Notes :
1.
2.
3.
4.
5.
DQ-to-I/O wiring may be changed within a byte.
DQ/DQS/DM/CKE/CS relationships are maintained as shown.
DQ/DQS/
resistors are 22 Ohms +/- 5%
BAx, Ax,
,
,
resistors are 5.1 Ohms +/- 5%
Address and control resistors are 22 Ohms +/- 5%
Serial PD
SCL
WP A0
SA0
A1
SA1
A2
SA2
SDA
REV 1.1
11/2005
4
NANYA reserves the right to change products and specifications without notice.
© NANYA TECHNOLOGY CORPORATION
NT1GT64U8HA0BN (Green)
1GB : 128M x 64
PC2-3200 / PC2-4200 / PC2-5300 Unbuffered DDR2 SO-DIMM
Serial Presence Detect
(Part 1 of 2)
SPD Entry Value
Byte
Description
DDR2-
400
-5A
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
Number of Serial PD Bytes Written during Production
Total Number of Bytes in Serial PD device
Fundamental Memory Type
Number of Row Addresses on Assembly
Number of Column Addresses on Assembly
Number of DIMM Ranks
Data Width of Assembly
Reserved
Voltage Interface Level of this Assembly
DDR2 SDRAM Device Cycle Time at CL=5
DDR2 SDRAM Device Access Time from Clock at CL=5
DIMM Configuration Type
Refresh Rate/Type
Primary DDR2 SDRAM Width
Error Checking DDR2 SDRAM Device Width
Reserved
DDR2 SDRAM Device Attributes: Burst Length Supported
DDR2 SDRAM Device Attributes: Number of Device Banks
DDR2 SDRAM Device Attributes: CAS Latencies Supported
DIMM Mechanical Characteristics
DDR2 SDRAM DIMM Type Information
DDR2 SDRAM Module Attributes:
DDR2 SDRAM Device Attributes: General
Minimum Clock Cycle at CL=4
Maximum Data Access Time from Clock at CL=4
Minimum Clock Cycle Time at CL=3
Maximum Data Access Time from Clock at CL=3
Minimum Row Precharge Time (t
RP
)
Minimum Row Active to Row Active delay (t
RRD
)
Minimum RAS to CAS delay (t
RCD
)
Minimum RAS Pulse Width (t
RAS
)
Module Bank Density
Address and Command Setup Time Before Clock (t
IS
)
Address and Command Hold Time After Clock (t
IH
)
Data Input Setup Time Before Clock (t
DS
)
Data Input Hold Time After Clock (t
DH
)
Write Recovery Time (t
WR
)
Internal Write to Read Command delay (t
WTR
)
Internal Read to Precharge delay (t
RTP
)
Reserved
Extension of Byte 41 t
RC
and Byte 42 t
RFC
Minimum Core Cycle Time (t
RC
)
10ns
0.35ns
0.15 ns
5ns
±0.6ns
5ns
0.6ns
DDR2-
533
-37B
128
256
DDR2-SDRAM
14
10
2 rank, Height = 30mm
X64
Undefined
SSTL_1.8
3.75ns
0.5ns
Non-Parity
SR/1x(7.8us)
X8
NA
Undefined
4,8
4
3/4/5
<4.10mm
Serial PD Data Entry
(Hexadecimal)
DDR2-
400
-5A
DDR2-
533
-37B
80
08
08
0E
0A
61
40
00
05
DDR2-
667
-3C
Note
DDR2-
667
-3C
3ns
0.45ns
50
60
3D
50
00
82
08
00
00
0C
04
38
01
04
00
01
30
45
Regular SODIMM (67.6mm)
Normal DIMM
Support weak driver
3.75ns
±0.5ns
5ns
0.6ns
15ns
7.5ns
15ns
45ns
512MB
0.25 ns
0.10 ns
15ns
7.5 ns
7.5ns
Undefined
The number below a decimal
point of t
RC
and t
RFC
are 0, t
RFC
is less than 256ns
60ns
7.5ns
28
0.2ns
0.05ns
0.175ns
35
47
15
27
0.475 ns 0.375 ns 0.325ns
0.275ns 0.225ns
3.75ns
±0.5ns
50
60
03
3D
50
50
60
3C
1E
3C
2D
80
25
37
10
22
3C
1E
1E
00
00
3C
1E
20
27
10
17
3D
50
REV 1.1
11/2005
5
NANYA reserves the right to change products and specifications without notice.
© NANYA TECHNOLOGY CORPORATION
ARM技术
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