Maximum Junction Temperature................... 150°C
Storage Temperature Range.......... –65°C to 150°C
Lead Temperature (Soldering, 10 sec) ......... 260°C
Note 1:
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum
Rating condition for extended periods may affect device reliability and lifetime.
Note 2:
The op amp supplies must be established simultaneously, with, or before, the application of any input signals.
Note 3:
The inputs are protected by ESD protection diodes to each power supply. If the input extends more than 500mV beyond the power supply, the input
current should be limited to less than 10mA.
Note 4:
A heat sink may be required to keep the junction temperature below the absolute maximum. This depends on the power supply voltage and how many
amplifiers are shorted. Thermal resistance varies with the amount of PC board metal connected to the package. The specified values are for short traces
connected to the leads.
ESD, Electrostatic Discharge Protection
Symbol
HBM
CDM
Parameter
Human Body Model ESD
Charged Device Model ESD
Condition
MIL-STD-883H Method 3015.8
JEDEC-EIA/JESD22-C101E
Minimum Level
8
2
Unit
kV
kV
Thermal Resistance
Package Type
5-Pin SOT23
8-Pin SOIC
8-Pin MSOP
14-Pin SOIC
14-Pin TSSOP
θ
JA
250
158
210
120
180
θ
JC
81
43
45
36
35
Unit
°C/W
°C/W
°C/W
°C/W
°C/W
2
Rev. A
www.3peakic.com
TP2401/TP2402
/ TP2404
Electrical Characteristics
20MHz Bandwidth, Low Noise CMOS Op‐amps
The specifications are at T
A
= 27°C. V
S
= +2.2 V to +5.5 V, or ±1.1 V to ±2.75 V, R
L
= 2kΩ, C
L
=100pF.Unless otherwise noted.
SYMBOL
V
OS
V
OS
TC
I
B
I
OS
V
n
e
n
i
n
C
IN
CMRR
V
CM
PSRR
A
VOL
V
OL
, V
OH
R
OUT
R
O
I
SC
V
DD
I
Q
PM
GM
GBWP
SR
FPBW
t
S
THD+N
X
talk
PARAMETER
Input Offset Voltage
Input Offset Voltage Drift
Input Bias Current
Input Offset Current
Input Voltage Noise
Input Voltage Noise Density
Input Current Noise
Input Capacitance
Common Mode Rejection Ratio
Common-mode Input Voltage
Range
Power Supply Rejection Ratio
Open-Loop Large Signal Gain
Output Swing from Supply Rail
Closed-Loop Output Impedance
Open-Loop Output Impedance
Output Short-Circuit Current
Supply Voltage
Quiescent Current per Amplifier
Phase Margin
Gain Margin
Gain-Bandwidth Product
Slew Rate
Full Power Bandwidth
Note 1
Settling Time, 0.1%
Settling Time, 0.01%
Total Harmonic Distortion and
Noise
Channel Separation
V
DD
= 5V
R
LOAD
= 1kΩ, C
LOAD
= 60pF
R
LOAD
= 1kΩ, C
LOAD
= 60pF
f = 1kHz
AV = 1, V
OUT
= 1.5V to 3.5V, C
LOAD
= 60pF,
R
LOAD
= 1kΩ
AV = –1, 1V Step
f = 1kHz, AV =1, RL = 2kΩ, VOUT = 1Vp-p
f = 1kHz, R
L
= 2kΩ
f = 0.1Hz to 10Hz
f = 1kHz
f = 1kHz
Differential
Common Mode
V
CM
= 2V to 3V
V
CM
= V
DD
/2
-40°C to 125°C
T
A
= 27 °C
T
A
= 85 °C
T
A
= 125 °C
CONDITIONS
MIN
-1
TYP
±0.3
1
0.3
150
300
0.001
2.0
7.3
2
7.76
6.87
100
V
+
-0.3
100
130
13
0.043
125
110
2.2
3.5
60
11
20
18
25
5.21
0.29
0.45
123
110
130
200
5.5
5
20
MAX
+1
2
UNITS
mV
μV/°C
pA
pA
pA
pA
μV
PP
nV/√Hz
fA/√Hz
pF
dB
V
dB
dB
mV
Ω
Ω
mA
V
mA
°
dB
MHz
V/μs
MHz
μs
dB
dB
80
V
–
-0.3
V
CM
= 2.5V, V
S
= 4V to 5V
R
LOAD
= 2kΩ
R
LOAD
= 2kΩ
G = 1, f =1MHz, I
OUT
= 0
f = 1kHz, I
OUT
= 0
Sink or source current
80
100
Note 1:
Full power bandwidth is calculated from the slew rate FPBW = SR/π • V
FPGA/CPLD
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