Silicon
N-Channel
Power MOSFET
R
○
CS3N150F A9R
General Description
：
CS3N150F A9R, the silicon N-channel Enhanced
VDMOSFETs, is obtained by the self-aligned planar Technology
which reduce the conduction loss, improve switching
performance and enhance the avalanche energy. The transistor
can be used in various power switching circuit for system
miniaturization and higher efficiency. The package form is
TO-220F, which accords with the RoHS standard.
V
DSS
I
D
P
D
(T
C
=25℃)
R
DS(ON)Typ
1500
3
32
5.0
V
A
W
Ω
Features：
l
Fast Switching
l
Low ON Resistance
(Rdson≤6.5Ω)
l
Low Gate Charge
(Typical Data: 37.6nC)
l
Low Reverse transfer capacitances
(Typical:2.8 pF)
l
100% Single Pulse avalanche energy Test
Applications
：
Power switch circuit of adaptor and charger.
Absolute
（T
J
= 25℃ unless otherwise specified）
：
Symbol
V
DSS
I
D
I
DM
a1
Parameter
Drain-to-Source Voltage
Continuous Drain Current T
C
= 25
°C
Continuous Drain Current T
C
= 100
°C
Pulsed Drain Current T
C
= 25
°C
Gate-to-Source Voltage
Rating
1500
3
1.8
12
±30
227
5.0
32
0.26
150，–55 to 150
300
Units
V
A
A
A
V
mJ
V/ns
W
W/℃
℃
℃
V
GS
E
AS
a2
a3
Single Pulse Avalanche Energy
Peak Diode Recovery dv/dt
Power Dissipation T
C
= 25
°C
Derating Factor above 25°C
Operating Junction and Storage Temperature Range
Maximum Temperature for Soldering
dv/dt
P
D
T
J
，T
stg
T
L
W U X I C H I N A R E S O U R C E S H U A J I N G M I C R O E L E C T R O N I C S C O . , LT D .
Pag e 1 of 1 0
2 0 1 9 V0 2
CS3N150F A9R
Electrical Characteristics
（T
J
= 25℃ unless otherwise specified）
：
OFF Characteristics
Symbol
V
DSS
ΔBV
DSS
/ΔT
J
I
DSS
I
GSS(F)
I
GSS(R)
Parameter
Drain to Source Breakdown Voltage
Bvdss Temperature Coefficient
Drain to Source Leakage Current
Gate to Source Forward Leakage
Gate to Source Reverse Leakage
R
○
Test Conditions
V
GS
=0V, I
D
=250µA
ID=250uA,Reference25℃
V
DS
=1500V, V
GS
= 0V,
T
J
= 25℃
V
DS
=1200V, V
GS
= 0V,
T
J
= 125℃
V
GS
=+30V
V
GS
=-30V
Rating
Min.
Typ.
Max.
Unit
s
V
V/℃
µA
µA
nA
nA
1500
--
--
--
--
--
--
1.5
--
--
--
--
--
--
25
500
100
-100
ON Characteristics
Symbol
R
DS(ON)
V
GS(TH)
Parameter
Drain-to-Source On-Resistance
Gate Threshold Voltage
Test Conditions
V
GS
=10V,I
D
=1.5A
V
DS
= V
GS
, I
D
= 250µA
Rating
Min.
Typ.
Max.
Units
Ω
V
--
3.0
5.0
--
6.5
5.0
Pulse width tp≤300µs,δ≤2%
Dynamic Characteristics
Symbol
g
fs
R
g
C
iss
C
oss
C
rss
Parameter
Forward Trans conductance
Gate resistance
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
V
GS
= 0V V
DS
= 25V
f = 1.0MHz
Test Conditions
V
DS
=30V, I
D
=1.5A
f = 1.0MHz
Rating
Min.
Typ.
Max.
Units
S
Ω
pF
--
--
--
--
--
4.5
4.0
2036
98
2.8
--
--
--
--
--
Resistive Switching Characteristics
Symbol
t
d(ON)
tr
t
d(OFF)
t
f
Q
g
Q
gs
Q
gd
Parameter
Turn-on Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Total Gate Charge
Gate to Source Charge
Gate to Drain (“Miller”)Charge
I
D
=3A V
DD
=750V
V
GS
= 10V
I
D
=3A V
DD
= 750V
R
G
=10Ω
Test Conditions
Rating
Min.
Typ.
Max.
Units
--
--
--
--
--
--
--
35.8
19.4
56
31.2
37.6
9.9
14.4
--
--
--
--
--
--
--
nC
ns
W U X I C H I N A R E S O U R C E S H U A J I N G M I C R O E L E C T R O N I C S C O . , LT D .
Pag e 2 of 1 0
2 0 1 9 V0 2
CS3N150F A9R
R
○
Source-Drain Diode Characteristics
Symbol
I
S
I
SM
V
SD
trr
Qrr
I
RRM
Parameter
Continuous Source Current (Body Diode)
Maximum Pulsed Current (Body Diode)
Diode Forward Voltage
Reverse Recovery Time
I
S
=3.0A,T
j
= 25℃
I
S
=3.0A,V
GS
=0V
Test
Conditions
T
C
= 25
°C
Rating
Min.
Typ.
Max.
Units
A
A
V
ns
µ
C
--
--
--
--
--
--
--
--
--
882
3
12
1.5
--
--
--
Reverse Recovery Charge
Reverse Recovery Current
dI
F
/dt=100A/us,
V
GS
=0V
6.5
14.7
A
Pulse width tp≤300µs,δ≤2%
Symbol
R
θ
JC
R
θ
JA
Parameter
Junction-to-Case
Junction-to-Ambient
Max.
3.8
62.5
Units
℃/W
℃/W
a1
a2
a3
：Repetitive
rating; pulse width limited by maximum junction temperature
：L=10mH,
I
D
=6.7A, Start T
J
=25℃
：I
SD
=3A,di/dt
≤100A/us,V
DD
≤BV
DS,
Start T
J
=25℃
W U X I C H I N A R E S O U R C E S H U A J I N G M I C R O E L E C T R O N I C S C O . , LT D .
Pag e 3 of 1 0
2 0 1 9 V0 2
CS3N150F A9R
Characteristics Curve：
R
○
Figure 1 Maximum Forward Bias Safe Operating Area
Figure 2 Maximum Power dissipation vs Case Temperature
Figure 3 Maximum Continuous Drain Current vs Case Temperature
Figure 4 Typical Output Characteristics
Figure 5 Maximum Effective Thermal Impedance , Junction to Case
W U X I C H I N A R E S O U R C E S H U A J I N G M I C R O E L E C T R O N I C S C O . , LT D .
Pag e 4 of 1 0
2 0 1 9 V0 2
CS3N150F A9R
R
○
Figure 6 Typical Transfer Characteristics
Figure 7 Typical Body Diode Transfer Characteristics
Figure 8 Typical Drain to Source ON Resistance
vs Drain Current
Figure 9 Typical Drian to Source on Resistance
vs Junction Temperature
W U X I C H I N A R E S O U R C E S H U A J I N G M I C R O E L E C T R O N I C S C O . , LT D .
Pag e 5 of 1 0
2 0 1 9 V0 2
FPGA/CPLD
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