Silicon N-Channel Power MOSFET
CS1N50 A3R
General Description
：
CS1N50 A3R, the silicon N-channel Enhanced
VDMOSFETs, is obtained by the self-aligned planar Technology
which reduce the conduction loss, improve switching
performance and enhance the avalanche energy. The transistor
can be used in various power switching circuit for system
miniaturization and higher efficiency. The package form is TO-251,
which accords with the RoHS standard.
V
DSS
I
D
P
D
(T
C
=25℃)
R
DS(ON)Typ
500
1
15
9.1
R
○
V
A
W
Ω
Features：
Fast Switching
Low ON Resistance
(Rdson≤10Ω)
Low Gate Charge
(Typical Data: 6.2nC)
Low Reverse transfer capacitances
(Typical:2.5pF)
100% Single Pulse avalanche energy Test
Applications
：
Power switch circuit of adaptor and charger.
Absolute
（Tc=
25℃ unless otherwise specified）
：
Symbol
V
DSS
I
D
I
DM
V
GS
E
AS
a1
Parameter
Drain-to-Source Voltage
Continuous Drain Current
Continuous Drain Current T
C
= 100 °
C
Pulsed Drain Current
Gate-to-Source Voltage
Rating
500
1
0.62
4
±30
20
5.0
15
0.12
150，–55 to 150
300
Units
V
A
A
A
V
mJ
V/ns
W
W/℃
℃
℃
a2
a3
Single Pulse Avalanche Energy
Peak Diode Recovery dv/dt
Power Dissipation
dv/dt
P
D
Derating Factor above 25°
C
Operating Junction and Storage Temperature Range
Maximum Temperature for Soldering
T
J
，T
stg
T
L
W U X I C H I N A R E S O U R C E S H U A J I N G M I C R O E L E C T R O N I C S C O . , LT D .
P ag e 1 of 10
2 0 1 7 V0 1
CS1N50 A3R
Electrical Characteristics
（Tc=
25℃ unless otherwise specified）
：
OFF Characteristics
Symbol
V
DSS
ΔBV
DSS
/ΔT
J
I
DSS
I
GSS(F)
I
GSS(R)
Parameter
Drain to Source Breakdown Voltage
Bvdss Temperature Coefficient
Drain to Source Leakage Current
Gate to Source Forward Leakage
Gate to Source Reverse Leakage
R
○
Test Conditions
V
GS
=0V, I
D
=250µA
ID=250uA,Reference25℃
V
DS
=500V, V
GS
= 0V,
T
a
= 25℃
V
DS
=400V, V
GS
= 0V,
T
a
= 125℃
V
GS
=+30V
V
GS
=-30V
Rating
Min.
Typ.
Max.
Unit
s
V
V/℃
µA
µA
nA
nA
500
--
--
--
--
--
--
0.6
--
--
--
--
--
--
1
100
100
-100
ON Characteristics
Symbol
R
DS(ON)
V
GS(TH)
Parameter
Drain-to-Source On-Resistance
Gate Threshold Voltage
Test Conditions
V
GS
=10V,I
D
=0.5A
V
DS
= V
GS
, I
D
= 250µA
Rating
Min.
Typ.
Max.
Units
Ω
V
--
2.0
9.1
--
10
4.0
Pulse width tp≤300µs,δ≤2%
Dynamic Characteristics
Symbol
g
fs
C
iss
C
oss
C
rss
Parameter
Forward Trans conductance
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
V
GS
= 0V V
DS
= 25V
f = 1.0MHz
Test Conditions
V
DS
=15V, I
D
=0.5A
Rating
Min.
Typ.
Max.
Units
S
pF
--
--
--
--
0.8
70
16
2.5
--
--
--
--
Resistive Switching Characteristics
Symbol
t
d(ON)
tr
t
d(OFF)
t
f
Q
g
Q
gs
Q
gd
Parameter
Turn-on Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Total Gate Charge
Gate to Source Charge
Gate to Drain (“Miller”)Charge
I
D
=1A V
DD
=400V
V
GS
= 10V
I
D
=1A V
DD
= 250V
R
G
=10Ω
Test Conditions
Rating
Min.
Typ.
Max.
Units
--
--
--
--
--
--
--
7.7
9.7
25.4
14.4
6.2
0.5
4.7
--
--
--
--
--
--
--
nC
ns
W U X I C H I N A R E S O U R C E S H U A J I N G M I C R O E L E C T R O N I C S C O . , LT D .
P ag e 2 of 10
2 0 1 7 V0 1
CS1N50 A3R
R
○
Source-Drain Diode Characteristics
Symbol
I
S
I
SM
V
SD
trr
Qrr
I
RRM
Parameter
Continuous Source Current (Body Diode)
Maximum Pulsed Current (Body Diode)
Diode Forward Voltage
Reverse Recovery Time
I
S
=1.0A,T
j
= 25℃
I
S
=1A,V
GS
=0V
Test Conditions
Rating
Min.
Typ.
Max.
Units
A
A
V
ns
nC
A
--
--
--
--
--
--
--
--
--
265
322
2.7
1
4
1.5
--
--
--
Reverse Recovery Charge
Reverse Recovery Current
dI
F
/dt=100A/us,
V
GS
=0V
Pulse width tp≤300µs,δ≤2%
Symbol
R
θ
JC
R
θ
JA
Parameter
Junction-to-Case
Junction-to-Ambient
Max.
8
100
Units
℃/W
℃/W
a1
a2
：Repetitive
rating; pulse width limited by maximum junction temperature
：L=10mH,
I
D
=2.0A, Start T
J
=25℃
a3
：I
SD
=1A,di/dt
≤100A/us,V
DD
≤BV
DS,
Start T
J
=25℃
W U X I C H I N A R E S O U R C E S H U A J I N G M I C R O E L E C T R O N I C S C O . , LT D .
P ag e 3 of 10
2 0 1 7 V0 1
CS1N50 A3R
Characteristics Curve：
R
○
Figure 1 Maximum Forward Bias Safe Operating Area
Figure 2 Maximum Power dissipation vs Case Temperature
Figure
4 Typical Output Characteristics
Figure 3 Maximum Continuous Drain Current vs Case Temperature
Figure 4 Typical Output Characteristics
Figure 5 Maximum Effective Thermal Impedance , Junction to Case
W U X I C H I N A R E S O U R C E S H U A J I N G M I C R O E L E C T R O N I C S C O . , LT D .
P ag e 4 of 10
2 0 1 7 V0 1
CS1N50 A3R
R
○
Figure 6 Typical Transfer Characteristics
Figure 7 Typical Body Diode Transfer Characteristics
Figure 8 Typical Drain to Source ON Resistance
vs Drain Current
Figure 9 Typical Drian to Source on Resistance
vs Junction Temperature
W U X I C H I N A R E S O U R C E S H U A J I N G M I C R O E L E C T R O N I C S C O . , LT D .
P ag e 5 of 10
2 0 1 7 V0 1
FPGA/CPLD
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