Silicon
N-Channel
Power MOSFET
R
○
CS60N12 A8
General Description
：
CS60N12
A8,
the
silicon
N-channel
Enhanced
VDMOSFETs, is obtained by advanced Trench Technology
which reduce the conduction loss, improve switching
performance and enhance the avalanche energy. The transistor
can be used in various power switching circuit for system
miniaturization and higher efficiency. The package form is
TO-220AB, which accords with the RoHS standard.
V
DSS
I
D
P
D
(T
C
=25℃)
R
DS(ON)Typ
120
60
198
15
V
A
W
mΩ
Features：
l
Fast Switching
l
Low ON Resistance
(Rdson≤20mΩ)
l
Low Gate Charge
l
Low Reverse transfer capacitances
(Typical:112.9pF)
l
100% Single Pulse avalanche energy Test
Applications
：
Power switch circuit of adaptor and charger.
Absolute
（T
J
= 25℃ unless otherwise specified）
：
Symbol
V
DSS
I
D
I
DM
a1
Parameter
Drain-to-Source Voltage
Continuous Drain Current T
C
= 25
°C
Continuous Drain Current T
C
= 100
°C
Pulsed Drain Current T
C
= 25
°C
Gate-to-Source Voltage
Rating
120
60
41
240
±20
397.8
198
1.584
150，–55 to 150
300
Units
V
A
A
A
V
mJ
W
W/℃
℃
℃
V
GS
E
AS
P
D
T
J
，T
stg
T
L
a2
Single Pulse Avalanche Energy
Power Dissipation T
C
= 25
°C
Derating Factor above 25°C
Operating Junction and Storage Temperature Range
Maximum Temperature for Soldering
W U X I C H I N A R E S O U R C E S H U A J I N G M I C R O E L E C T R O N I C S C O . , LT D .
Pag e 1 of 1 0
2 0 2 0 V0 1
CS60N12 A8
Electrical Characteristics
（T
J
= 25℃ unless otherwise specified）
：
OFF Characteristics
Symbol
V
DSS
I
DSS
I
GSS(F)
I
GSS(R)
Parameter
Drain to Source Breakdown Voltage
Drain to Source Leakage Current
Gate to Source Forward Leakage
Gate to Source Reverse Leakage
R
○
Test Conditions
V
GS
=0V, I
D
=250µA
V
DS
=120V, V
GS
= 0V,
T
J
= 25℃
V
DS
=96V, V
GS
= 0V,
T
J
= 125℃
V
GS
=+20V
V
GS
=-20V
Rating
Min.
Typ.
Max.
Units
V
µA
µA
nA
nA
120
--
--
--
--
--
--
--
--
--
--
1
100
100
-100
ON Characteristics
Symbol
R
DS(ON)
V
GS(TH)
Parameter
Drain-to-Source On-Resistance
V
GS
=4.5V,I
D
=15A
Test Conditions
V
GS
=10V,I
D
=25A
Rating
Min.
Typ.
Max.
Units
mΩ
mΩ
V
--
1.0
15
15.5
--
20
23
2.5
Gate Threshold Voltage
V
DS
= V
GS
, I
D
= 250µA
Pulse width tp≤300µs,δ≤2%
Dynamic Characteristics
Symbol
R
g
C
iss
C
oss
C
rss
Parameter
Gate resistance
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
V
GS
=0V，V
DS
=60V
f=1.0MHz
Test Conditions
V
GS
=0V, V
DS
=0V, f=1MHz
Rating
Min.
Typ.
Max.
Units
Ω
pF
--
--
--
--
1.2
4281
188.2
112.9
--
--
--
--
Resistive Switching Characteristics
Symbol
t
d(ON)
tr
t
d(OFF)
t
f
Q
g
Q
gs
Q
gd
Parameter
Turn-on Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Total Gate Charge
Gate to Source Charge
Gate to Drain (“Miller”)Charge
V
GS
=10V，V
DD
=96V
I
D
=30A
V
GS
=10V，R
G
=4.7Ω
V
DD
=60V，I
D
=30A
Test Conditions
Rating
Min.
Typ.
Max.
Units
--
--
--
--
--
--
--
20.5
15
97
105
96.8
10.2
25.7
--
--
--
--
--
--
--
nC
ns
W U X I C H I N A R E S O U R C E S H U A J I N G M I C R O E L E C T R O N I C S C O . , LT D .
Pag e 2 of 1 0
2 0 2 0 V0 1
CS60N12 A8
R
○
Source-Drain Diode Characteristics
Symbol
I
S
I
SM
V
SD
trr
Qrr
I
RRM
Parameter
Continuous Source Current (Body Diode)
Maximum Pulsed Current (Body Diode)
Diode Forward Voltage
Reverse Recovery Time
I
S
=30A,T
j
= 25℃
I
S
=25A,V
GS
=0V
Test Conditions
Rating
Min.
Typ.
Max.
Units
A
A
V
ns
nC
A
--
--
--
--
dI
F
/dt=100A/us,
--
--
--
54
97.7
3.6
60
240
1.2
--
--
--
Reverse Recovery Charge
Reverse Recovery Current
--
--
Pulse width tp≤300µs,δ≤2%
Symbol
R
θ
JC
R
θ
JA
Parameter
Junction-to-Case
Junction-to-Ambient
Max.
0.63
62.5
Units
℃/W
℃/W
a1
a2
：Repetitive
rating; pulse width limited by maximum junction temperature
：L=0.5mH,
I
D
=39.89A, Start T
J
=25℃
W U X I C H I N A R E S O U R C E S H U A J I N G M I C R O E L E C T R O N I C S C O . , LT D .
Pag e 3 of 1 0
2 0 2 0 V0 1
CS60N12 A8
Characteristics Curve：
R
○
Figure1. Maximum Forward Bias Safe Operating Area
Figure2. Maximum Power Dissipation vs Case
Temperature
Figure3. Maximum Continuous Drain Current vs
Case Temperature
Figure 4. Typical Output Characteristics
Figure5. Maximum Effective Transient Thermal Impedance, Junction-to-Case
W U X I C H I N A R E S O U R C E S H U A J I N G M I C R O E L E C T R O N I C S C O . , LT D .
Pag e 4 of 1 0
2 0 2 0 V0 1
CS60N12 A8
R
○
Figure 6. Typical Transfer Characteristics
Figure 7. Typical Body Diode Transfer Characteristics
Figure 8. Drain-to-Source On Resistance vs Drain Current
Figure 9. Nomalized on Resistance vs Junction
Temperature
Figure 10. Nomalized Theshold Voltage vs
Junction Temperature
Figure 11. Nomalized Breakdown Voltage vs
Junction Temperature
Pag e 5 of 1 0
W U X I C H I N A R E S O U R C E S H U A J I N G M I C R O E L E C T R O N I C S C O . , LT D .
2 0 2 0 V0 1
FPGA/CPLD
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
