NT56V6650C0T
64Mb : x4
PC133 / PC100 Synchronous DRAM
Contents
Revision Log
............................................................................................................................................................................................. 02
Table of Contents
.................................................................................................................................................................................... 03
Description................................................................................................................................................................................................
05
Features.....................................................................................................................................................................................................05
Product Family
........................................................................................................................................................................................05
Pin Assignment
........................................................................................................................................................................................05
Pin Description.........................................................................................................................................................................................07
Functional Block Diagram
.....................................................................................................................................................................08
Ordering Information..............................................................................................................................................................................09
DC Characteristics..................................................................................................................................................................................
10
Absolute Maximum Ratings
............................................................................................................................................................. 10
Recommended DC Operating Conditions
........................................................................................................................................ 10
Capacitance
.................................................................................................................................................................................... 10
DC Electrical Characteristics
..........................................................................................................................................................11
DC Output Load Circuit
...................................................................................................................................................................11
Operating, Standby, and Refresh Currents
....................................................................................................................................11
AC Characteristics..................................................................................................................................................................................
13
AC Output Load Circuits
..................................................................................................................................................................13
AC Timing Parameters...........................................................................................................................................................................
14
Clock and Clock Enable Parameters
...............................................................................................................................................14
Common Parameters
....................................................................................................................................................................... 14
Mode Register Set Cycle
................................................................................................................................................................ 14
Read Cycle
..................................................................................................................................................................................... 15
Refresh Cycle
.................................................................................................................................................................................15
Write Cycle
..................................................................................................................................................................................... 15
Clock Frequency and Latency
........................................................................................................................................................15
Command Truth Table............................................................................................................................................................................
17
DEVICE OPERATIONS..............................................................................................................................................................................23
Power On and Initialization
............................................................................................................................................................. 23
Programming the Mode Register
..................................................................................................................................................... 23
Mode Register Definition
................................................................................................................................................................. 23
Burst Mode Operation
.....................................................................................................................................................................25
Burst Length and Sequence
...........................................................................................................................................................25
Bank Activate Command
................................................................................................................................................................. 26
Bank Select
..................................................................................................................................................................................... 26
Read and Write Access Modes
...................................................................................................................................................... 27
Burst Read Command
.....................................................................................................................................................................27
Read Interrupted by a Read
............................................................................................................................................................ 28
Read Interrupted by a Write
............................................................................................................................................................ 29
Burst Write Command
.....................................................................................................................................................................29
Write Interrupted by a Write
............................................................................................................................................................ 30
Write Interrupted by a Read
............................................................................................................................................................ 30
Burst Stop Command
......................................................................................................................................................................31
Auto-Precharge Operation
............................................................................................................................................................. 32
Precharge Command
......................................................................................................................................................................36
Bank Selection for Precharge by Address Bits
.............................................................................................................................. 36
Precharge Termination
....................................................................................................................................................................38
Automatic Refresh Command
.........................................................................................................................................................39
Self Refresh Command
...................................................................................................................................................................39
Power Down Mode
......................................................................................................................................................................... 40
Data Mask
.......................................................................................................................................................................................40
No Operation Command
..................................................................................................................................................................41
REV 1.1 June, 2000
3
© NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT56V6650C0T
64Mb : x4
PC133 / PC100 Synchronous DRAM
Description
The NT56V6650C0T is four-bank Synchronous DRAMs organized as 4Mbit x 4 I/O x 4 Bank . The devices achieve high-speed data transfer
rates of up to 133MHz by employing a pipeline chip architecture that synchronizes the output data to a system clock. The chip is fabricated
with NANYA advanced 64Mbit single transistor CMOS DRAM process technology.
The device is designed to comply with all JEDEC standards set for synchronous DRAM products, both electrically and mechanically. All of
the control, address, and data input/output (I/O or DQ) circuits are synchronized with the positive edge of an externally supplied clock.
/RAS, /CAS, /WE, and /CS are pulsed signals which are examined at the positive edge of each externally applied clock (CLK). Internal chip
operating modes are defined by combinations of these signals and a command decoder initiates the necessary timings for each operation. A
fourteen bit address bus accepts address data in the conventional /RAS /CAS multiplexing style. Twelve row addresses (A0-A11) and two
bank select addresses (A12, A13) are strobed with /RAS. Ten column addresses (A0-A9) plus bank select addresses and A10 are strobed
with /CAS.
Prior to any access operation, the /CAS latency, burst length, and burst sequence must be programmed into the device by address inputs
A0-A9 during a mode register set cycle. In addition, it is possible to program a multiple burst sequence with single write cycle for write
through cache operation.
Operating the four memory banks in an interleave fashion allows random access operation to occur at a higher rate than is possible with
standard DRAMs. A sequential and gapless data rate of up to 133MHz is possible depending on burst length, /CAS latency, and speed
grade of the device. Simultaneous operation of both decks of a stacked device is allowed, depending on the operation being done. Auto
Refresh (CBR), Self Refresh, and Low Power operation are supported.
Feature
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JEDEC standard 3.3V± 0.3V Power Supply
LVTTL compatible inputs and outputs
Four Banks controlled by Bank Selects(A12/A13)
Single Pulsed /RAS Interface
Fully Synchronous to Positive Clock Edge
MRS cycle with address key programmability for :
- CAS Latency ( 2, 3 )
- Burst Length ( 1, 2, 4, 8 & Full-page )
- Burst Type ( Sequential or Interleave )
Multiple Burst Read with Single Write Option
Automatic and Controlled Precharge Command
Data Mask for Read/Write control
Auto Refresh (CBR) and Self Refresh
Suspend Mode and Power Down Mode
Standard Power operation
4096 refresh cycles/64ms
Random Column Address every CLK (1-N Rule)
Package:54-pin 400 mil TSOP
-Type II
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Product Family
Part NO.
NT56V6650C0T-7
NT56V6650C0T-75B
NT56V6650C0T-75
NT56V6650C0T-8A
NT56V6650C0T-8B
16M x 4
Organization
Speed ( MHz@CL-tRP-tRCD)
143 MHz @ 3-3-3
133 MHz @ 3-3-3
133 MHz @ 3-3-3
125 MHz @ 3-3-3
125 MHz @ 3-3-3
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100 MHz @ 2-2-2
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100MHZ @ 2-2-2
100MHz @ 3-2-2
Interface
Package
LVTTL
54pin
TSOP II
REV 1.1 June, 2000
5
© NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
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