杭州中科微电子有限公司
集成了
EEPROM
的
单通道、单色随屏显示器
概述
AT7456E
是一款集成了
EEPROM
的单通道、单色随屏
显示发生器，集成了视频驱动器、同步分离器、视频分离开
关以及
EEPROM，
提高了系统的集成度，
有效降½了系统成
本。
AT7456E
采用符合
NTSC
和
PAL
制式的
512
个用户可
编程字符，适合于全球市场。
AT7456E
½够方便地以任意字符、尺寸显示各种信息，
例如公司标识、常用图½、时间、日期等。
AT7456E
预先装½½了
512
个字符和图½，并可以通过
SPI
兼容串行接口进行在线编程。
AT7456E
提供
28
引脚
TSSOP
封装，
工½温度范围
（-40℃
~+85℃）
。
字符大小为
12×18
象素
闪烁、反色和背景控制字符
可逐行设½亮度
最多显示
16
行×30 列字符
视频驱动器输出带有衰减补偿
LOS、
VSYNC
、
HSYNC
兼容于
NTSC
和
PAL
SPI
兼容串行接口
出厂时带有预先编程的字符组
和时钟输出
内½同步发生器，同时可外部输入复合同步信号
特性
512
个用户定义字符或图½存储于
EEPROM
应用
安全监控系统
安全监控摄像机
工业监控
室内娱乐系统
手持测量仪器
消费类电子
注：AT7456E 兼容
MAX7456，½应用程序需做一些调整，具½见应用信息一节（Page35）
。
AT7456E
HTSSOP28
定购信息
中文
电路功½结构框图
1
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杭州中科微电子有限公司
极限工½条件：
AVDD to AGND ........................................................-0.3V to +6V
DVDD to DGND........................................................-0.3V to +6V
PVDD to PGND.........................................................-0.3V to +6V
AGND to DGND.....................................................-0.3V to +0.3V
AGND to PGND.....................................................-0.3V to +0.3V
DGND to PGND.....................................................-0.3V to +0.3V
VIN, VOUT, SAG to AGND......................-0.3V to (V
AVDD
+ 0.3V)
CLKIN, CLKOUT, XFB to DGND ............-0.3V to (V
DVDD
+ 0.3V)
SDIN, SCLK,
CS
, SDOUT to DGND........-0.3V to (V
DVDD
+ 0.3V)
Maximum Continuous Current into V
OUT
........................±100mA
Continuous Power Dissipation (T
A
= +70°C)
28-Pin TSSOP (derate 27mW/°C above +70°C).......2162mW*
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range .............................-60°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
HSYNC
,
VSYNC
, LOS to AGND .........................-0.3V to +6V
RESET
to AGND .....................................-0.3V to (V
AVDD
+ 0.3V)
电特性参数：
(V
AVDD
= +3.15V to +5.25V, V
DVDD
= +3.15V to +5.25V, V
PVDD
= +3.15V to +5.25V, T
A
= T
MIN
to T
MAX
. Typical values are at V
AVDD
= V
DVDD
= V
PVDD
= +5V, T
A
= +25°C, unless otherwise noted.) (Note 1)
PARAMETER
POWER SUPPLIES
Analog Supply Voltage
Digital Supply Voltage
Driver Supply Voltage
Analog Supply Current
V
AVDD
V
DVDD
V
PVDD
I
AVDD
V
IN
= 1V
P-P
(100% white flat field signal),
VOUT load, R
L
= 150Ω
V
IN
= 1V
P-P
(100% white flat field signal),
VOUT load, R
L
= 150Ω
V
IN
= 1V
P-P
(100% white flat field signal),
VOUT load, R
L
= 150Ω
3.15
3.15
3.15
2.0
5
5
5
2.2
5.25
5.25
5.25
2.5
V
V
V
mA
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Digital Supply Current
I
DVDD
16
43.1
60
mA
Driver Supply Current
NONVOLATILE MEMORY
Data Retention
Endurance
DIGITAL INPUTS (
CS
, SDIN,
Input High Voltage
Input Low Voltage
Input Hysteresis
Input Leakage Current
Input Capacitance
I
PVDD
4.0
6.0
10
mA
T
A
= +25°C
T
A
= +25°C
100
100,000
Years
Stores
RESET
, SCLK)
V
IH
V
IL
V
HYS
V
IN
= 0 or V
DVDD
C
IN
5
2.0
2.1
1.4
50
±10
0.8
V
V
mV
uA
pF
DIGITAL OUTPUTS (SDOUT, CLKOUT,
Output High Voltage
Output Low Voltage
Tri-State Leakage Current
CLOCK INPUT (CLKIN)
Clock Frequency
Clock-Pulse High
Clock-Pulse Low
Input High Voltage
V
OH
V
OL
HSYNC
,
VSYNC
, LOS)
I
SOURCE
= 4mA (SDOUT, CLKOUT)
I
SINK
= 4mA
SDOUT,
2.4
4.88
0.16
0.45
±10
V
V
uA
CS
= V
DVDD
27
14
14
18.4
18.8
MHz
ns
ns
V
0.65 x V
DVDD
2
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杭州中科微电子有限公司
Input Low Voltage
PARAMETER
Input Leakage Current
CLOCK OUTPUT (CLKOUT)
Duty Cycle
Rise Time
Fall Time
VIDEO CHARACTERISTICS
DC Power-Supply Rejection
V
AVDD
= V
DVDD
= V
PVDD
= 5V; V
IN
= 1V
P-P
,
measured at VOUT
V
AVDD
= V
DVDD
= V
PVDD
= 5V; V
IN
= 1V
P-P
,
AC Power-Supply Rejection
measured at VOUT; f = 5MHz; power-supply
ripple = 0.2V
P-P
Short-Circuit Current
Line-Time Distortion
Output Impedance
Gain
Black Level
Input-Voltage Operating Range
Input-Voltage Sync Detection
Range
Maximum Output-Voltage Swing
Output-Voltage Sync Tip Level
Large Signal Bandwidth (0.2dB)
VIN to VOUT Delay
Differential Gain
Differential Phase
OSD White Level
Horizontal Pixel Jitter
Video Clamp Settling Time
OSD CHARACTERISTICS
OSD Rise Time
OSD insertion mux register OSDM[5,4,3] =
011b
OSD insertion mux register OSDM[5,4,3] =
011b
OSD insertion mux register OSDM[2,1,0] =
011b
68
ns
DG
DP
VOUT 100% white level with respect to black
level
Between consecutive horizontal lines
1.25
BW
V
OUT
= 2V
P-P
, Figures 1a, 1b
V
IN
V
INSD
V
OUT
LTD
Z
OUT
VOUT to PGND
Figures 1a, 1b
Figures 1a, 1b
Figures 1a, 1b
At VOUT, Figures 1a, 1b
Figures 1a, 3 (Note 2)
Figures 1a, 3 (Note 3)
Figures 1a, 1b
0.5
0.5
2.4
2.66
0.7
6
20
0.5
0.5
1.33
24
32
1.45
1.89
0.22
2.0
2.11
200
230
0.5
mA
%
Ω
V/V
V
V
P-P
V
P-P
V
P-P
V
MHz
ns
%
Degrees
V
ns
Lines
30
dB
40
dB
5pF and 10kΩto DGND
5pF and 10kΩto DGND
5pF and 10kΩto DGND
40
51.6
3.2
3.6
60
%
ns
ns
SYMBOL
CONDITIONS
V
IN
= 0V or V
DVDD
MIN
0.3 x V
DVDD
TYP
±5
MAX
±50
V
UNITS
uA
1.26 AGND+1.5
1.2
2.0
OSD Fall Time
68
ns
OSD Insertion Mux Switch Time
110
ns
3
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杭州中科微电子有限公司
时间特性参数：
(V
AVDD
= +3.15V to +5.25V, V
DVDD
= +3.15V to +5.25V, V
PVDD
= +3.15V to +5.25V, T
A
= T
MIN
to T
MAX
. Typical values are at V
AVDD
= V
DVDD
= V
PVDD
= +5V, T
A
= +25°C, unless otherwise noted.) (Note 1)
PARAMETER
SPI TIMING
SCLK Period
SCLK Pulse-Width High
SCLK Pulse-Width Low
t
CP
t
CH
t
CL
t
CSS0
t
CSH0
t
CSS1
t
CSH1
t
CSW
t
DS
t
DH
t
DO1
t
DO2
t
DO3
t
DO4
20pF to ground
20pF to ground
20pF to ground
20pF to ground
100
40
40
30
0
30
0
100
30
0
25
0
300
20
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
CS
Fall to SCLK Rise Setup
CS
Fall After SCLK Rise Hold
CS
Rise to SCLK Setup
CS
Rise After SCLK Hold
CS
Pulse-Width High
SDIN to SCLK Setup
SDIN to SCLK Hold
SDOUT Valid Before SCLK
SDOUT Valid After SCLK
CS
High to SDOUT High Impedance
CS
Low to SDOUT Logic Level
LOS,
HSYNC
,
VSYNC
, AND LOS TIMING
VSYNC
,
HSYNC
VSYNC
Falling
VSYNC
Rising
Valid before CLKOUT Rising Edge
VOUT Sync to
Edge Delay
VOUT Sync to
Edge Delay
t
DOV
20pF to ground
NTSC external sync mode, Figure 4
PAL external sync mode, Figure 6
NTSC external sync mode, Figure 4
PAL external sync mode, Figure 6
NTSC internal sync mode, Figure 5
PAL internal sync mode, Figure 7
NTSC internal sync mode, Figure 5
PAL internal sync mode, Figure 7
NTSC and PAL external sync mode,
Figure 8
NTSC and PAL external sync mode,
Figure 8
NTSC and PAL internal sync mode,
Figure 9
NTSC and PAL internal sync mode,
Figure 9
Power-up delay
27MHz CLK
30
375
400
400
425
40
45
32
30
310
ns
t
VOUT-VSF
ns
ns
t
VOUT-VSR
VSYNC
Falling Edge to VOUT
Sync Delay
t
VSF-VOUT
ns
VSYNC
Rising Edge to VOUT Sync
Delay
VOUT Sync to
Edge Delay
VOUT Sync to
Edge Delay
t
VSR-VOUT
ns
HSYNC
Falling
HSYNC
Rising
t
VOUT-HSF
ns
t
VOUT-HSR
325
ns
HSYNC
Falling Edge to VOUT
Sync Delay
t
HSF-VOUT
115
ns
HSYNC
Rising Edge to VOUT
Sync Delay
All Supplies High to
NVM Write Busy
t
HSR-VOUT
t
PUD
t
NVW
115
50
3.4/4.2
ns
ms
ms
CS
Low
4
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杭州中科微电子有限公司
Note 1: See the standard test circuits of Figure 1. R
L
= 75 , unless otherwise specified. All digital input signals
are timed from a voltage level of (V
IH
+ V
IL
) / 2. All parameters are tested at T
A
= +85°C and values through temperature
range are guaranteed by design.
Note 2: The input-voltage operating range is the input range over which the output signal parameters are guaranteed
(Figure 3).
Note 3: The input-voltage sync detection range is the input composite video range over which an input sync signal is
properly detected and the OSD signal appears at VOUT. However, the output voltage specifications are not guaranteed
for input signals exceeding the maximum specified in the input operating voltage range (Figure 3).
图
1.
标准测试电路
图
2.
典型工½电路
5
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