Two-wire
Serial EEPROM
K24C02C / K24C04 / K24C08C / K24C16B
Spring 2011
K24C02C/K24C04/K24C08C/K24C16B
2K bits (256 X 8) / 4K bits (512 X 8) / 8K bits (1024 X 8) / 16K bits (2048 X 8)
Two-wire Serial EEPROM
Features
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Wide Voltage Operation
- V
CC
= 1.8V to 5.5V
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Operating Ambient Temperature: -40
•
C to +85
•
C
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Internally Organized:
- K24C02C, 256 X 8 (2K bits)
- K24C04, 512 X 8 (4K bits)
- K24C08C, 1024 X 8 (8K bits)
- K24C16B, 2048 X 8 (16K bits)
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1 MHz (5V), 400 kHz (1.8V, 2.5V, 2.7V) Compatibility
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Write Protect Pin for Hardware Data Protection
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8-byte Page (2K), 16-byte Page (4K, 8K, 16K) Write Modes
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Partial Page Writes Allowed
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Self-timed Write Cycle (5 ms max)
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High-reliability
- Endurance: 1 Million Write Cycles
- Data Retention: 100 Years
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Two-wire Serial Interface
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Schmitt Trigger, Filtered Inputs for Noise Suppression
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Bidirectional Data Transfer Protocol
General Description
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8-lead PDIP/SOP/MSOP/TSSOP, 8-pad DFN, and SOT23-5
packages
The K24C02C/K24C04/K24C08C/K24C16B provides 2048/4096/8192/16384 bits of serial electrically erasable and
programmable read-only memory (EEPROM) organized as 256/512/1024/2048 words of 8 bits each. The device is
optimized for use in many industrial and commercial applications where low-power and low-voltage operation are
essential. The K24C02C/K24C04/K24C08C/K24C16B is available in space-saving 8-lead PDIP , 8-lead SOP, 8-lead
MSOP, 8-lead TSSOP, 8-pad DFN, and SOT23-5 packages and is accessed via a two-wire serial interface.
Pin Configuration
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Table 1: Pin Configuration
Pin Name
Founctions
A0 - A2
SDA
SCL
WP
GND
V
CC
Address Inputs
Serial Data
Serial Clock Input
Write Protect
Ground
Power Supply
V
CC
WP
SCL
SDA
8-pad DFN
SOT23-5
8
7
6
5
1
2
3
4
A0
A1
A2
GND
SCL
GND
SDA
1
2
3
5
WP
4
V
CC
Bottom view
8-lead PDIP
8-lead SOP
8-lead TSSOP
8-lead MSOP
A0
A1
A2
GND
1
2
3
4
8
7
6
5
V
CC
WP
SCL
SDA
A0
A1
A2
GND
1
2
3
4
8
7
6
5
V
CC
WP
SCL
SDA
A0
A1
A2
GND
1
2
3
4
8
7
6
5
V
CC
WP
SCL
SDA
A0
A1
A2
GND
1
2
3
4
8
7
6
5
V
CC
WP
SCL
SDA
Spring 2011
V1.3
.
001
.
K24C02C/K24C04/K24C08C/K24C16B
2K bits (256 X 8) / 4K bits (512 X 8) / 8K bits (1024 X 8) / 16K bits (2048 X 8)
Two-wire Serial EEPROM
Block Diagram
V
CC
GND
WP
SCL
SDA
START STOP
LOGIC
EN
SERIAL CONTROL
LOGIC
LOAD
COMP
DEVICE ADDRESS
COMPARATOR
HIGH VOLTAGE
PUMP/TIMING
DATA RECOVERY
A0
A1
A2
LOAD
INC
DATA WORD
ADDRESS COUNTER
X DECODER
EEPROM
Y DECODER
SERIAL MUX
DIN
DOUT/ACKNOWLEDGE
DOUT
Spring 2011
V1.3
.
002
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K24C02C/K24C04/K24C08C/K24C16B
2K bits (256 X 8) / 4K bits (512 X 8) / 8K bits (1024 X 8) / 16K bits (2048 X 8)
Two-wire Serial EEPROM
Pin Descriptions
DEVICE/PAGE ADDRESSES (A2, A1 and A0):
The A2, A1 and A0 pins are device address inputs that are hard
wired for the K24C02C. Eight 2K devices may be addressed on a single bus system (device addressing is discussed
in detail under the Device Addressing section).
The K24C04 uses the A2 and A1 inputs for hard wire addressing and a total of four 4K devices may be addressed on a
single bus system. The A0 pin is a no connect and can be connected to ground.
The K24C08C only uses the A2 input for hardwire addressing and a total of two 8K devices may be addressed on a
single bus system. The A0 and A1 pins are no connects and can be connected to ground.
The K24C16B does not use the device address pins, which limits the number of devices on a single bus to one. The
A0, A1, and A2 pins are no connects and can be connected to ground.
SERIAL DATA (SDA):
The SDA pin is bi-directional for serial data transfer. This pin is open-drain driven and may be
wire-ORed with any number of other open-drain or open- collector devices.
SERIAL CLOCK (SCL):
The SCL input is used to positive edge clock data into each EEPROM device and negative
edge clock data out of each device.
WRITE PROTECT (WP):
The K24C02C/K24C04/K24C08C/K24C16B has a W rite Protect pin that provides hardware
data protection. The Write Protect pin allows normal read/write operations when connected to ground (GND). When the
Write Protect pin is connected to V
CC
, the write protection feature is enabled and operates as shown in the following
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Table 2: Write Protect
Part of the Array Protected
WP Pin Status
K24C02C
Full (2K) Array
K24C04
Full (4K) Array
K24C08C
Full (8K) Array
K24C16B
Full (16K) Array
At V
CC
At GND
Normal Read / Write Operations
Memory Organization
K24C02C, 2K SERIAL EEPROM:
Internally organized with 32 pages of 8 bytes each, the 2K requires an 8-bit
data word address for random word addressing.
K24C04, 4K SERIAL EEPROM:
Internally organized with 32 pages of 16 bytes each, the 4K requires a 9-bit data
word address for random word addressing.
K24C08C, 8K SERIAL EEPROM:
Internally organized with 64 pages of 16 bytes each, the 8K requires a 10-bit
data word address for random word addressing.
K24C16B, 16K SERIAL EEPROM:
Internally organized with 128 pages of 16 bytes each, the 16K requires an 11-bit
data word address for random word addressing.
Spring 2011
V1.3
.
003
.
K24C02C/K24C04/K24C08C/K24C16B
2K bits (256 X 8) / 4K bits (512 X 8) / 8K bits (1024 X 8) / 16K bits (2048 X 8)
Two-wire Serial EEPROM
Device Operation
CLOCK and DATA TRANSITIONS:
The SDA pin is normally pulled high with an external device. Data on the SDA
pin may change only during SCL low time periods (see to Figure 1 on page 4). Data changes during SCL high periods
will indicate a start or stop condition as defined below.
START CONDITION:
A high-to-low transition of SDA with SCL high is a start condition which must precede any other
command (see to Figure 2 on page 4).
STOP CONDITION:
A low-to-high transition of SDA with SCL high is a stop condition. After a read sequence, the stop
command will place the EEPROM in a standby power mode (see Figure 2 on page 4).
ACKNOWLEDGE:
All addresses and data words are serially transmitted to and from the EEPROM in 8-bit words. The
EEPROM sends a "0" to acknowledge that it has received each word. This happens during the ninth clock cycle.
STANDBY MODE:
The K24C02C/K24C04/K24C08C/K24C16B features a low-power standby mode which is enabled:
(a) upon power-up and (b) after the receipt of the STOP bit and the completion of any internal operations
MEMORY RESET:
After an interruption in protocol, power loss or system reset, any two-wire part can be reset by
following these steps:
1.
2.
3.
Clock up to 9 cycles.
Look for SDA high in each cycle while SCL is high.
Create a start condition.
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Figure 1: Data Validity
SDA
SCL
DATA STABLE
DATA
CHANGE
DATA STABLE
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Figure 2: Start and Stop Definition
SDA
SCL
START
STOP
Spring 2011
V1.3
.
004
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