ESD5Z5VL
ESD5Z5VL
1-Line, Uni-directional, Ultra-low Capacitance
Transient Voltage Suppressors
http//:www.sh-willsemi.com
Descriptions
The ESD5Z5VL is an ultra-low capacitance TVS (Transient
Voltage Suppressor) designed to protect high speed data
interfaces. It has been specifically designed to protect
sensitive electronic components which are connected to data
and transmission lines from over-stress caused by ESD
(Electrostatic Discharge).
The ESD5Z5VL incorporates one pair of ultra- low
capacitance steering diodes plus a TVS diode.
The ESD5Z5VL may be used to provide ESD protection up to
±20kV
(contact
and
air
discharge)
according
to
Pin1
Pin2
SOD-523
IEC61000-4-2, and withstand peak pulse current up to 4A
(8/20μs) according to IEC61000-4-5.
The ESD5Z5VL is available in SOD-523 package. Standard
products are Pb-free and Halogen-free.
Circuit diagram
Features
Stand-off voltage: 5V max.
Transient protection for each line according to
IEC61000-4-2 (ESD): ±20kV (contact and air discharge)
IEC61000-4-4 (EFT): 40A (5/50ns)
IEC61000-4-5 (surge): 4A (8/20μs)
Ultra-low capacitance: C
J
= 1.2pF typ.
Ultra-low leakage current: I
R
<1nA typ.
Low clamping voltage: V
CL
= 18V typ. @ I
PP
= 16A (TLP)
Solid-state silicon technology
Pin1
* x
Marking (Top View)
.
Pin2
x = Device code
* = Month code ( A~Z)
Order information
Device
Package
SOD-523
Shipping
3000/Tape&Reel
Applications
USB 2.0 and USB 3.0
HDMI 1.3 and HDMI 1.4
SATA and eSATA
DVI
IEEE 1394
PCI Express
Portable Electronics and Notebooks
1
ESD5Z5VL-2/TR
Will Semiconductor Ltd.
Revision 1.3, 2014/11/11
ESD5Z5VL
Absolute maximum ratings
Parameter
Peak pulse power (t
p
= 8/20μs)
Peak pulse current (t
p
= 8/20μs)
ESD according to IEC61000-4-2 air discharge
ESD according to IEC61000-4-2 contact discharge
Junction temperature
Operating temperature
Lead temperature
Storage temperature
Symbol
P
pk
I
PP
V
ESD
T
J
T
OP
T
L
T
STG
Rating
60
4
±20
±20
125
-40~85
260
-55~150
Unit
W
A
kV
o
o
o
o
C
C
C
C
Electrical characteristics
(T
A
= 25
o
C, unless otherwise noted)
Parameter
Reverse maximum working voltage
Reverse leakage current
Reverse breakdown voltage
Forward voltage
Clamping voltage
1)
1)
Symbol
V
RWM
I
R
V
BR
V
F
V
CL
R
DYN
V
CL
C
J
Condition
Min.
Typ.
Max.
5.0
Unit
V
nA
V
V
V
Ω
V
RWM
= 5V
I
BR
= 1mA
I
F
= 10mA
I
PP
= 16A, t
p
= 100ns
7.0
0.6
<1
8.0
0.9
18.0
0.57
100
9.0
1.2
Dynamic resistance
Clamping voltage
2)
I
PP
= 1A, t
p
= 8/20μs
I
PP
= 4A, t
p
= 8/20μs
V
R
= 0V, f = 1MHz
1.2
11
15
1.6
V
V
pF
Junction capacitance
Notes:
1)
TLP parameter: Z
0
= 50 Ω , t
p
= 100ns, t
r
= 2ns, averaging window from 60ns to 80ns. R
DYN
is calculated from 4A to
16A.
Non-repetitive current pulse, according to IEC61000-4-5.
2)
Will Semiconductor Ltd.
2
Revision 1.3, 2014/11/11
ESD5Z5VL
Typical characteristics
(T
A
= 25
o
C, unless otherwise noted)
100
90
Front time: T
1
= 1.25
×
T = 8µs
Time to half-value:
T
2
= 20µs
Peak pulse current (%)
100
90
50
T
2
Current (%)
10
10
0
0
T
T
1
20
Time (µs)
30ns
t
r
= 0.7~1ns
60ns
t
Time (ns)
8/20μs waveform per IEC61000-4-5
Contact discharge current waveform per IEC61000-4-2
C
J
- Junction capacitance (uniformization)
1.24
V
C
- Clamping voltage (V)
14
Pulse waveform: t
p
= 8/20µs
1.22
12
1.20
f = 1MHz
V
AC
= 50mV
10
1.18
8
0
1
2
3
4
I
PP
- Peak pulse current (A)
5
1.16
0
1
2
3
4
V
R
- Reverse voltage (V)
5
Clamping voltage vs. Peak pulse current
Capacitance vs. Reverse voltage
1000
100
Peak pulse power (W)
100
% of Rated power
80
60
40
20
10
1
0
1
10
100
Pulse time (µs)
1000
0
25
50
75
100
125
150
T
A
- Ambient temperature (
o
C)
Power derating vs. Ambient temperature
Non-repetitive peak pulse power vs. Pulse time
Will Semiconductor Ltd.
3
Revision 1.3, 2014/11/11
ESD5Z5VL
Package outline dimensions
SOD-523
Symbol
A
A1
b
c
D
E
E1
E2
L
θ
Dimensions in millimeter
Min.
0.510
0.500
0.250
0.080
0.750
1.100
1.500
Typ.
0.640
0.600
0.300
0.115
0.800
1.200
1.600
0.200 Ref
0.010
0.040
7° Ref
0.070
Max.
0.770
0.700
0.350
0.150
0.850
1.300
1.700
Recommend land pattern (Unit: mm)
Note: This land pattern is for your reference
only. Actual pad layouts may vary depending
on application.
Will Semiconductor Ltd.
5
Revision 1.3, 2014/11/11
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