WD3153
WD3153
3-Channel LED Driver
Http//:www.sh-willsemi.com
Descriptions
The WD3153 is a 3-channel LED driver designed to
produce variety of lighting effects. The device has a
program memory for creating variety of lighting
sequences. When the program memory has been
loaded, the WD3153 can operate independently
without processor control.
Three independent LED channels have accurate
programmable current sinks, from 0mA to 25mA with 5
steps and 8-bit flexible PWM control. Each channel
can be configured into each of the three program
execution engines. Program execution engines have
program
memory
for
creating
desired
lighting
sequences with PWM control.
LED0
LED1
LED2
INTN
VCC
1
2
3
4
5
10
9
SCL
SDA
CHRG
SET
NC
GND
8
7
6
Pin configuration (Top view)
3153
WDYW
Features
Supply voltage: 2.4V to 5.5V
Three independently programmable LED outputs
with 8-bit PWM control and 3-bit current setting
(from 0mA to 25mA)
Autonomous
2
DFN2X2-10L
3153
= Device code
= Year code
= Week code
Marking
operation
with
three
program
Y
W
execution engines
Direct I C register control for lighting
I C Compatible Interface
Power supply support 1.8V to 5.5V
Data transfers up to 400kbps
Device
2
Order information
Package
DFN2X2-10L
Shipping
3000/Reel&Tape
WD3153D-10/TR
INTN interrupt function
Typical LED output saturation voltage 80mV
LED output current accuracy ±2% and current
matching ±1%
Built-in oscillator with ±5% accuracy
Support charging indication under low battery
condition
Directly start up breathing light on LED0
Breathing period: 5s or continuous
Operating current: 80uA
Less than 1uA in shut down mode
Operating temperature: -40℃ to 85℃
ESD HBM 4kV
DFN2X2-10L package
Applications
1
Smart Phones
Tablets
Indicator lights
Nov. 2017 - Rev. 1.2
Low power consumption
Will Semiconductor Ltd.
WD3153
Typical applications
VBAT
CHRG
VCC
GND
VBAT
1uF
VBUS
30K
CHRG
VCC
GND
VBAT
1uF
Charger
10K
SET
VIO
4.7KΩ
*3
SET
VIO
4.7KΩ
*3
WD3153
R
LED0
LED1
LED2
INTN
SCL
SDA
G
B
CPU
INTN
SCL
SDA
R
G
B
WD3153
LED0
LED1
LED2
INTN
SCL
SDA
CPU
INTN
SCL
SDA
VBAT
VBAT
Fig1 Charging Indicator Application
Fig2 Adapter Plug In Indicator Application
Pin descriptions
No.
1
2
3
4
5
6
7
Name
LED0
LED1
LED2
INTN
VCC
NC
SET
I
I/O
Analog
Analog
Analog
Open drain
Power
Description
LED driver current sink terminal
LED driver current sink terminal
LED driver current sink terminal
Interrupt output
2.4V~5.5V power supply
Not internally connected
Charge indicator set.
0: LED0 output 5mA/5S period
1: LED0 output 5mA continuous
Charge indicator input. Internal pull-down resistor of 15KΩ
between CHRG and GND.
I C serial interface data input/output. 1.8V/5.5V compatible
I C serial interface clock. 1.8V/5.5V compatible
Connect to ground.
2
2
8
9
10
EP
CHRG
SDA
SCL
GND
I
I/O
I
Ground
Block diagram
VBG
VCC
SET
CHRG
OSC
UVLO
OTP
Control
Logic
I2C
REG
LED0
INTN
SCL
SDA
Constant
Current
LED
Driver
LED1
LED2
GND
Will Semiconductor Ltd.
2
Nov. 2017 - Rev. 1.2
WD3153
Absolute maximum ratings
(1)
Parameter
Power supply VCC
Analog pins (LED0, LED1, LED2)
Digital pins (SDA, SCL, INTN)
Storage temperature T
stg
Junction temperature T
JMAX
Maximum lead temperature
Junction-to-ambient thermal resistance (DFN10L)
ESD HBM
Latch-up
(1)
MIN
-0.3
-0.3
-0.3
-65
MAX
6.0
6.0
VCC+0.3V
with 6.0 max
150
150
260
45
Unit
V
V
V
℃
℃
℃
℃/W
kV
mA
-4
-450
4
450
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These
are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated
under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for
extended periods may affect device reliability.
Recommended Operating Conditions
Parameter
Power supply VCC
Digital pins
Junction temperature T
J
Ambient temperature T
A
MIN
2.4
1.8
-40
-40
MAX
5.5
VCC
125
85
Unit
V
V
℃
℃
Will Semiconductor Ltd.
3
Nov. 2017 - Rev. 1.2
WD3153
Electronics Characteristics
Unless otherwise specified, TA = 25℃ and VCC = 3.6V.
Symbol
I
SD
I
SB
Description
Shut down current
Standby current
Test Conditions
CHIPEN=0 (device off)
CHIPEN=1 (device on);
LE0~2=0 (all LEDs off)
CHIPEN=1 (device on);
LE0~2=1 (all LEDs on);
LCFG0~2=03h (all LEDs set
to 15mA);
Internal
LCFG0~2=04h
LCFG0~2=03h
MIN
TYP
0.1
35
MAX
1
50
Unit
uA
uA
I
CC
Operating current
80
120
uA
F
OSC
Oscillator frequency
-5
24.25
14.55
9.7
4.85
-1
80
237.5
475
250
500
25
15
10
5
0
5
25.75
15.45
10.3
5.15
+1
100
262.5
525
%
LED driver (LED0, LED1, LED2) electrical characteristics (GCR=01h, PWM0~2=FFh)
I
MAX
Maximum sink current
LCFG0~2=02h
LCFG0~2=01h
LCFG0~2=00h
mA
I
match
V
SAT
F
LED
(2)
Matching
(2)
Saturation voltage
(3)
PWM switching frequency
LCFG0~2=03h, 15mA Set
LCFG0~2=03h
PWM_HF=0
PWM_HF=1
%
mV
Hz
Hz
Output current accuracy is the difference between the actual value of the output current and programmed value of
this current. Matching is the maximum difference from the average. For the constant current outputs on the part, the
following are determined: the maximum output current (MAX), the minimum output current (MIN), and the average
output current of all outputs (AVG). Two matching numbers are calculated: (MAX - AVG)/AVG and (AVG - MIN)/AVG.
The largest number of the two (worst case) is considered the matching figure. Note that some manufacturers have
different definitions in use.
(3)
Saturation voltage is defined as the voltage when the LED current has dropped 10% from the set value.
Will Semiconductor Ltd.
4
Nov. 2017 - Rev. 1.2
WD3153
Logic interface characteristics
Unless otherwise specified: limits for typical values are for TA = 25℃ and minimum and maximum limits apply over the
operating ambient temperature range (-40℃ < TA < 85℃); VCC=3.6V and range (2.4V < VCC < 5.5V).
Symbol
V
DD_I2C
V
IH
V
IL
I
IH
I
IL
V
OL
I
L
2
Description
Power supply range for I C
Input high level
Input low level
High level input current
Low level input current
Output low level (I
OUT
= 3mA)
Output leakage current
I C clock frequency
Bus-free time between a STOP and a START condition
Hold time (repeated) START condition
Clock low time
Clock high time
Setup time for a repeated START condition
Data hold time
Data setup time
Rise time of SCL
Fall time of SCL
Set-up time for STOP condition
SCL input deglitch
SDA input deglitch
Capacitive load for each bus line
2
2
2
MIN
1.65
1.2
TYP
MAX
5.5
Unit
V
V
Logic input SCL and SDA characteristics
0.6
5
5
0.3
0.5
1
400
1.3
0.6
1.3
0.6
1.3
0.05
0.1
0.3
0.3
0.6
200
250
400
V
nA
nA
V
uA
kHz
uS
uS
uS
uS
uS
uS
uS
uS
uS
uS
nS
nS
pF
Logic output SDA characteristics
I C timing requirements
(4)
F
SCL
t
BUF
t
HD,STA
t
LOW
t
HIGH
t
SU,STA
t
HD,DAT
t
SU,DAT
t
R
t
F
t
SU,STO
T
SP
C
b
(4)
Specification is ensured by design and is not tested in production.
Fig4 is the timing parameters of I C interface (SCL, SDA).
Stop
Start
Start
Stop
SDA
t
BUF
t
LOW
t
F
t
HIGH
T
DEG
VIH
VIL
VIH
VIL
t
HD,STA
t
R
t
HD,DAT
t
SU,DAT
2
SCL
t
SU,STA
t
SU,STO
Fig4 I C timing parameters
Will Semiconductor Ltd.
5
Nov. 2017 - Rev. 1.2
微控制器 MCU
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