UNISONIC TECHNOLOGIES CO., LTD
UC3842A/3843A
CURRENT MODE PWM
CONTROL CIRCUITS
DESCRIPTION
The UTC
UC3842A/3843A
provide the necessary functions to
implement off-line or DC to DC fixed frequency current mode ,
controlled switching circuits with minimal external components.
LINEAR INTEGRATED CIRCUIT
FEATURES
*Low Start Up Current ( Typical 0.12mA )
*Automatic Feed Forward Compensation
*Pulse-by-Pulse Current Limiting
*Under-voltage Lockout with Hysteresis
*Double Pulse Suppression
*High Current Totem Pole Output to Drive MOSFET Directly
*Internally Trimmed Band Gap Reference
*500kHz Operation
ORDERING INFORMATION
Ordering Number
Lead Free
UC3842AL-D08-T
UC3842AL-S08-R
UC3842AL-S08-T
UC3843AL-D08-T
UC3843AL-S08-R
UC3843AL-S08-T
Halogen Free
UC3842AP-D08-T
UC3842AP-S08-R
UC3842AP-S08-T
UC3843AP-D08-T
UC3843AP-S08-R
UC3843AP-S08-T
Package
DIP-8
SOP-8
SOP-8
DIP-8
SOP-8
SOP-8
Packing
Tube
Tape Reel
Tube
Tube
Tape Reel
Tube
www.unisonic.com.tw
Copyright © 2012 Unisonic Technologies Co., Ltd
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QW-R103-002.G
UC3842A/3843A
PIN CONFIGURATION
COMP
1
2
3
4
LINEAR INTEGRATED CIRCUIT
8
7
6
5
V
REF
V
CC
V
FB
Current Sense
RT/CT
Output
GND
BLOCK DIAGRAM
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QW-R103-002.G
UC3842A/3843A
LINEAR INTEGRATED CIRCUIT
ABSOLUTE MAXIMUM RATINGS
(T
A
=25℃, unless otherwise specified)
PARAMETER
SYMBOL
RATINGS
UNIT
Supply Voltage(Low Impedance Source)
V
CC
30
V
Supply Voltage(I
CC
<30mA)
V
CC
Self Limiting
V
Analog Inputs (Pin 2,3)
V
I(ANA)
-0.3 ~ +6.3
V
Output Current (Peak )
I
O(PEAK)
±1
A
Error Amplifier Output Sink Current
I
SINK(EA)
10
mA
Output Energy (Capacity Load)
5
μJ
DIP-8
1250
Power Dissipation( T
A
≦25℃)
mW
P
D
SOP-8
800
Derated at T
A
>25℃
mW/℃
8
℃
Junction Temperature
T
J
+150
℃
Storage Temperature
T
STG
-65 ~ +150
Note Absolute maximum ratings are those values beyond which the device which the device could be permanently
damaged. Absolute maximum ratings are stress ratings only and functional device operation is not implied.
ELECTRICAL CHARACTERISTICS
(0℃≦T
A
≦70℃,
V
CC
=15V, R
T
=10kΩ, C
T
=3.3nF, unless otherwise specified)
PARAMETER
REFERENCE SECTION
Output Voltage
Line Regulation
Load Regulation
Temperature Stability
Total Output Variation
Output Noise Voltage
Long Term Stability
Output Short Circuit
OSCILLATOR SECTION
Initial Accuracy
Voltage Stability
Temperature Stability
Amplitude
ERROR AMPLIFIER SECTION
Input Voltage
Input Bias Current
AVOL
Unity Gain Bandwidth
PSRR
Output Sink Current
Output Source Current
V
OUT
High
V
OUT
Low
SYMBOL
V
REF
ΔV
REF
ΔV
REF
TEST CONDITIONS
T
J
=25℃,I
OUT
=1mA
12≦V
IN
25V
1≦I
OUT
=20mA
(Note 1)
Line, Load, Temp (Note 1)
10Hz≦f≦10kHz,T
J
=25℃ (Note 1)
T
A
=25℃,1000Hrs (Note 1)
MIN
4.9
TYP
5
6
6
0.2
50
5
-100
52
0.2
5
1.7
2.50
-0.3
90
1
70
6
-0.8
6
0.7
MAX
5.1
20
25
0.4
5.18
25
-180
57
1
UNIT
V
mV
mV
mV/℃
V
μV
mV
mA
kHz
%
%
V
V
μA
dB
MHz
dB
mA
mA
V
V
4.82
V
OSC
I
SC
f
Δf/ΔV
CC
V
OSC
V
I(EA)
I
I(BIAS)
-30
T
J
=25℃
12≦V
CC
≦25V
T
MIN
≦T
A
≦T
MAX
(Note 1)
V
PIN4
peak to peak
V
PIN1
=2.5V
2V
≦V
OUT
≦4V
T
J
=25℃ (Note 1)
I
2
≦V
CC
≦25V
V
PIN2
=2.7V,V
PIN1
=1.1V
V
PIN2
=2.3V,V
PIN1
=5V
V
PIN2
=2.3V, R
L
=15kΩ to GND
V
PIN2
=2.7V,V
PIN1
=1.1V
47
2.42
60
0.7
60
2
-0.5
5
2.58
-2
I
O(SINK)
I
O(SOURCE)
V
OH
V
OL
1.1
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QW-R103-002.G
UC3842A/3843A
ELECTRICAL CHARACTERISTICS(Cont.)
PARAMETER
CURRENT SENSE SECTION
Gain
Maximum Input signal
PSRR
Input Bias Current
Delay to Output
OUTPUT SECTION
Low
SYMBOL
G
V
V
I(MAX)
I
BIAS
V
PIN3
=0 to 2V
V
OL
LINEAR INTEGRATED CIRCUIT
TEST CONDITIONS
(Note 2, 3)
V
PIN1
=5V( Note 2)
12V≦V
CC
≦25V
MIN
2.85
0.9
TYP
3
1
70
-2
150
0.1
1.5
13.5
13.5
50
50
16
8.4
10
7.6
97
MAX
3.15
1.1
-10
300
0.4
2.2
UNIT
V/V
V
dB
μA
ns
V
V
V
V
ns
ns
V
V
V
V
%
%
mA
mA
V
I
O(SINK)
=20mA
I
O(SINK)
=200mA
Output Level
I
O(SOURCE)
=20mA
High
V
OH
I
O(SOURCE)
=200mA
T
J
=25℃,C
L
=1nF (Note 1)
Rise Time
t
R
T
J
=25℃,C
L
=1nF (Note 1)
Fall Time
t
F
UNDER-VOLTAGE LOCKOUT OUTPUT SECTION
3842A
Start Threshold
V
TH(ST)
3843A
3842A
Min. Operating Voltage
V
OPR(MIN)
After Turn On
3843A
PWM SECTION
MAX
D
(MAX)
Duty Cycle
MIN
D
(MIN)
TOTAL STANDBY CURRENT
Start-up Current
I
ST
Operating Supply Current
I
CC(OPR)
V
PIN2
=V
PIN3
=0V
V
CC
Zener Voltage
V
z
I
CC
=25mA
Note:1. These parameters, although guaranteed, are not 100% tested in production.
2. Parameters measured at trip point of latch with V
PIN 2
=0.
3. Gain defined as:
13
12
150
150
17.5
9
11.5
8.2
100
0
0.3
17
14.5
7.8
8.5
7
95
0.12
11
34
4. Adjust V
CC
above the start threshold before setting at 15V.
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QW-R103-002.G
UC3842A/3843A
OPEN-LOOP LABORATORY TEST FIXTURE
LINEAR INTEGRATED CIRCUIT
High peak current associated with capacity loads necessitate careful grounding techniques. Timing and bypass
capacitors should be connected close to Pin 5 in single point GND. The transistor and 5kΩ potentio-meter are used
to sample the oscillator waveform and apply an adjustable Ramp to Pin 3.
UNDER-VOLTAGE LOCKOUT
During Under-Voltage Lockout, the output driver is biased to a high impedance state. Pin 6 should be shunt to
GND with a bleeder resistor to prevent activating the power switch with output leakage currents.
ERROR AMPLIFIER CONFIGURATION
2.5V
0.5mA
Zi
Zf
2
1
Error amplifier can source or sink up to 0.5mA
UNISONIC TECHNOLOGIES CO., LTD
www.unisonic.com.tw
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QW-R103-002.G
嵌入式系统
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