®
RT9040
DDR Termination Regulator
General Description
The RT9040 is a sink/source tracking termination regulator.
It is specifically designed for low-cost and low-external
component count systems. The RT9040 possesses a high
speed operating amplifier that provides fast load transient
response and only requires a minimum 20μF of ceramic
output capacitance. The RT9040 supports remote sensing
functions and all features required to power the DDRI /
DDRII / DDRIII and Low Power DDRIII VTT bus termination
according to the JEDEC specification. In addition, the
RT9040 provides an open drain PGOOD signal to monitor
the output regulation and an EN signal that can be used
to discharge VTT during S3 (suspend to RAM) for DDR
applications .
The RT9040 is available in the thermal efficient WDFN-
10L 3x3 package.
Features
V
IN
Input Voltage Range : 1.1V to 3.5V
V
CNTL
Input Voltage Range : 2.375V to 5.5V
MLCC Stable
PGOOD to Monitor Output Regulation
±
10mA Reference (REFOUT)
Meet DDRI, DDRII JEDEC Spec Supports DDRIII, Low
Power DDRIII VTT Application
Soft Start Function UVLO and OCP
UVLO and OCP Protection
Thermal Shutdown
RoHS Compliant and Halogen Free
Application
Notebook/Desktop/Server
Telecom/Datacom, GSM Base Station, LCD-TV/PDP-
TV ,Copier/Printer, Set-Top Box
Ordering Information
RT9040
(2)
Pin 1 Orientation
(2) : Quadrant 2, Follow EIA-481-D
Package Type
QW : WDFN-10L 3x3 (W-Type)
Lead Plating System
G : Green (Halogen Free and Pb Free)
Z : ECO (Ecological Element with
Halogen Free and Pb free)
Note :
Richtek products are :
½
Pin Configurations
(TOP VIEW)
REFIN
VIN
VOUT
PGND
SENSE
GND
1
2
3
4
5
10
9
8
7
6
11
VCNTL
PGOOD
GND
EN
REFOUT
WDFN-10L 3x3
Marking Information
RT9040GQW(2)
G4= : Product Code
RoHS compliant and compatible with the current require-
ments of IPC/JEDEC J-STD-020.
Suitable for use in SnPb or Pb-free soldering processes.
G4=YM
DNN
YMDNN : Date Code
½
RT9040ZQW(2)
G4 : Product Code
G4 YM
DNN
YMDNN : Date Code
Copyright
©
2014 Richtek Technology Corporation. All rights reserved.
is a registered trademark of Richtek Technology Corporation.
DS9040-04 January 2014
www.richtek.com
1
RT9040
Typical Application Circuit
RT9040
V
IN
2
R1
10k
C1
10µF x 2
R2
10k
C2
1nF
6
C3
0.1µF
Chip Enable
1
VIN
REFIN
PGOOD
9
VOUT 3
SENSE 5
REFOUT
PGND
GND
4
VCNTL
10
R3
100k
C4
4.7µF
VCNTL
2.5V/3.3V/5V
Power Good Indicator
V
OUT
C5
10µF x 3
REFOUT
7 EN
8, 11 (Exposed Pad)
Functional Pin Description
Pin No.
1
2
3
4
5
6
7
Pin Name
REFIN
VIN
VOUT
PGND
SENSE
REFOUT
EN
Pin Function
Reference Input.
Supply Voltage for the LDO.
Power Output for the LDO.
Power Ground Output for the LDO.
Voltage Sense Output for the LDO. Connect to positive terminal of the output
capacitor or the load.
Reference Output. Connect to GND through 0.1uF ceramic capacitor.
Chip Enable. For DDR VTT application, connect EN to SLP_S3. For any other
application(s), use EN as the ON/OFF function.
Signal Ground. Connect to negative terminal of the output capacitor. The exposed
pad must be soldered to a large PCB and connected to GND for maximum power
dissipation.
PGOOD Output. Indicates regulation. Connect to an internal open drain
N-MOSFET.
2.5V, 3.3V or 5V power supply. A ceramic decoupling capacitor with a value
between 1F and 4.7F is required.
8,
GND
11 (Exposed Pad)
9
10
PGOOD
VCNTL
Function Block Diagram
EN VCNTL
REFIN
Control
Logic
Thermal
Protection
VIN
Buffer
REFOUT
+
OCP
-
SENSE
VOUT
PGOOD
Power
Good
GND
-
OP
+
Driver
+
OCP
-
PGND
Copyright
©
2014 Richtek Technology Corporation. All rights reserved.
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
2
DS9040-04 January 2014
RT9040
Absolute Maximum Ratings
(Note 1)
6V
6V
1.429W
70°C/W
8.2°C/W
Supply Input Voltage, V
IN
, REFIN, VCNTL --------------------------------------------------------------------------
Enable Voltage, EN -------------------------------------------------------------------------------------------------------
Power Dissipation, P
D
@ T
A
= 25°C
WDFN-10L 3x3 -------------------------------------------------------------------------------------------------------------
Package Thermal Resistance (Note 2)
WDFN-10L 3x3,
θ
JA
-------------------------------------------------------------------------------------------------------
WDFN-10L 3x3,
θ
JC
-------------------------------------------------------------------------------------------------------
Lead Temperature (Soldering, 10 sec.) ------------------------------------------------------------------------------- 260°C
Junction Temperature ----------------------------------------------------------------------------------------------------- 150°C
Storage Temperature Range --------------------------------------------------------------------------------------------
−
65°C to 150°C
ESD Susceptibility (Note 3)
HBM (Human Body Model) ---------------------------------------------------------------------------------------------- 2kV
MM (Machine Model) ----------------------------------------------------------------------------------------------------- 200V
(Note 4)
Recommended Operating Conditions
Supply Input Voltage, VCNTL ------------------------------------------------------------------------------------------ 2.375V to 5.5V
Supply Input Voltage, V
IN
------------------------------------------------------------------------------------------------ 1.1V to 3.5V
Junction Temperature Range --------------------------------------------------------------------------------------------
−
40°C to 125°C
Ambient Temperature Range --------------------------------------------------------------------------------------------
−
40°C to 85°C
Electrical Characteristics
(V
IN
= 1.8V, V
EN
= VCNTL = 3.3V, V
REFIN
= 0.9V, V
SENSE
= 0.9V, C
OUT
= 10uF x 3, T
A
= 25°C, unless otherwise specification)
Parameter
Supply Current
VCNTL Supply Current
VCNTL Shutdown
Current
VIN Supply Current
VIN Shutdown Current
Input Current
Symbol
I
VCNTL
I
SHDN_VCNTL
I
VIN
I
SHDN_VIN
Test Conditions
V
EN
= 3.3V, No Load
V
EN
= 0V, V
REFIN
= 0, No Load
V
EN
= 0V, V
REFIN
> 0.4V, No Load
V
EN
= 3.3V, No Load
V
EN
= 0V, No Load
Min
--
--
--
--
--
Typ
0.9
65
200
--
0.1
Max
2
80
500
2
50
Unit
mA
A
mA
A
REFIN Input Current
I
REFIN
V
EN
= 3.3 V
--
--
1
A
Output
VIN = 2.5 V, V
REFOUT
= 1.25 V
(DDRI), I
OUT
= 0A
Offset Voltage of Output
DC Voltage
V
VOTOL
VIN = 1.8 V, V
REFOUT
= 0.9V
(DDRII), I
OUT
= 0A
VIN = 1.5 V, V
REFOUT
= 0.75V
(DDRIII), I
OUT
= 0A
VOUT Load Regulation
V
LOAD
–2A < I
OUT
< 2A
--
10
--
10
--
10
15
1.25
--
0.9
--
0.75
--
--
--
10
--
10
--
10
15
V
mV
V
mV
V
mV
mV
Copyright
©
2014 Richtek Technology Corporation. All rights reserved.
is a registered trademark of Richtek Technology Corporation.
DS9040-04 January 2014
www.richtek.com
3
RT9040
Parameter
Symbol
VOUT Source Current
I
LIM_VOUT_sr
Limit
VOUT Sink Current
I
LIM_VOUT_sk
Limit
VOUT Discharge
R
DISCHARGE
Resistance
Power Good Comparator
VOUT PGOOD
Threshold
PGOOD Startup Delay
Output Low Voltage
PGOOD Bad Delay
Leakage Current
REFIN and REFOUT
REFIN Voltage Range
REFIN Under Voltage
Lockout
V
REFIN
V
UVLO_REFIN
REFIN Rising
Hysteresis
10mA
< I
REFOUT
< 10mA, V
REFIN
= 1.25 V
10mA
< I
REFOUT
< 10mA, V
REFIN
= 0.9 V
10mA
< I
REFOUT
< 10mA, V
REFIN
= 0.75V
V
REFOUT
= 0V
V
REFOUT
= V
IN
0.5
360
--
15
15
15
10
10
--
390
20
--
--
--
40
40
1.8
420
--
15
15
15
--
--
mA
mA
mV
V
mV
V
TH_PGOOD
Tpgdelay1
V
LOW_PGOOD
Tpgdealy2
I
LEAKAGE_PGOOD
Test Conditions
V
CNTL
= 5V (V
OUT
in PGOOD
window)
V
CNTL
= 5V (V
OUT
in PGOOD
window)
V
REFIN
= 0V, V
OUT
= 0.3V,
V
EN
= 0V
PGOOD window lower threshold
with respect to REFOUT
PGOOD Hysteresis
Startup rising edge, V
SENSE
within
15% of REFOUT
I
SINK
= 4mA
V
SENSE
is outside of the ±20%
PGOOD window
V
SENSE
= V
REFIN
(PGOOD high
impedance), PGOOD = VCNTL +
0.2 V
Min
3.5
3.5
--
Typ
--
--
18
Max
5.5
5.5
25
Unit
A
A
23.5
--
--
--
--
--
20
5
2
--
10
--
17.5
--
--
0.4
--
1
%
ms
V
s
A
REFOUT Voltage
Tolerance to VREFIN
V
TOL_REFOUT
REFOUT Source
I
LIM_REFOUT_sr
Current Limit
REFOUT Sink Current
I
LIM_REFOUT_sk
Limit
UVLO / EN Logic Threshold
UVLO Threshold
High-Level Input
Voltage
Low-Level Input
Voltage
Hysteresis Voltage
Logic Input Leakage
Current
Thermal Shutdown
Thermal Shutdown
Threshold
V
UVLO_VCNTL
V
IN_H
V
IN_L
V
EN_hys
I
LEAKAGE_EN
Wake up
Hysteresis
Enable
Enable
Enable
Enable
2.2
--
1.7
--
--
1
2.3
50
--
--
0.5
--
2.375
--
--
0.3
--
1
V
mV
V
V
V
A
T
SD
Shutdown Temperature
Hysteresis
--
--
160
25
--
--
C
Copyright
©
2014 Richtek Technology Corporation. All rights reserved.
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
4
DS9040-04 January 2014
RT9040
Note 1.
Stresses beyond those listed
“Absolute
Maximum Ratings” may cause permanent damage to the device. These are
stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in
the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may
affect device reliability.
Note 2.
θ
JA
is measured at T
A
= 25°C on a high effective thermal conductivity four-layer test board per JEDEC 51-7.
θ
JC
is
measured at the exposed pad of the package.
Note 3.
Devices are ESD sensitive. Handling precaution is recommended.
Note 4.
The device is not guaranteed to function outside its operating conditions.
Copyright
©
2014 Richtek Technology Corporation. All rights reserved.
is a registered trademark of Richtek Technology Corporation.
DS9040-04 January 2014
www.richtek.com
5
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