P6SMBJ SERIES
SURFACE MOUNT TRANSIENT VOLTAGE SUPPRESSOR POWER 600 Watt
STAND-OFF VOLTAGE
5 to 220 Volt
Recongnized File # E210467
FEATURES
• For surface mounted applications in order to optimize board space
• Glass passivated junction
• Low inductance
• Plastic package has Underwriters Laboratory Flammability
Classification 94V-O
• High temperature soldering : 260°C /10 seconds at terminals
• ESD IEC-61000-4-2 Air + 30kV, Contact + 30kV
• Lead free in compliance with EU RoHS 2.0
• Green molding compound as per IEC 61249 standard
MECHANICAL DATA
• Case: JEDEC DO-214AA,Molded plastic over passivated junction.
• Terminals: Solder plated,solderable per MIL-STD-750,Method 2026
• Polarity: Color band denotes cathode end
• Standard Packaging: 12mm tape (EIA-481)
• Weight: 0.003 ounces, 0.092 grams
DEVICES FOR BIPOLAR APPLICATIONS
For Bidirectional use C or CA Suffix for types P6SMBJ5.0 thru types P6SMBJ220.
Electrical characteristics apply in both directions.
MAXIMUM RATINGS AND CHARACTERISTICS
Rating at 25°Cambient temperature unless otherwise specified. Resistive or inductive load, 60Hz.
For Capacitive load derate current by 20%.
Rating
Peak Pulse Power Dissipation on tp=10/1000μs waveform (Notes 1,2, Fig.1)
Peak Forward Surge Current 8.3ms single half sine-wave
superimposed on rated load (Notes 2,3)
Peak Pulse Current on tp=10/1000μs waveform (Notes 1) Fig.3
Typical Thermal Resistance Junction to Air (Notes 2)
ESD IEC-61000-4-2 (Air)
ESD IEC-61000-4-2 (Contact)
Operating Junction and Storage Temperature Range
Symbol
P
PP
I
FSM
I
PPM
R
θJA
V
ESD
T
J
,T
STG
Value
600
100
see Table 1
60
+30
+30
-55 to +150
Units
Watts
Amps
Amps
O
C/ W
kV
O
C
NOTES :
1. Non-repetitive current pulse, per Fig.3 and derated above T
A
= 25
O
C per Fig. 2.
2. Mounted on 5mm
2
(0.13mm thick) land areas.
3. Measured on 8.3ms, single half sine-wave or equivalent s quare wave, duty cycle = 4 pulses per minute maximum.
4. A transient suppressor is selected according to the working peak reverse voltage (V
RWM
), which should be equal to or
greater than the DC or continuous peak operating voltage level.
July 25,2018-REV.14
PAGE . 1
FPGA/CPLD
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