PPJA3417
20V P-Channel Enhancement Mode MOSFET
Voltage
Features
-20 V
Current
-5.2A
SC-59
Unit : inch(mm)
R
DS(ON)
, V
GS
@-4.5V, I
D
@-5.2A<35mΩ
R
DS(ON)
, V
GS
@-2.5V, I
D
@-3.7A<40mΩ
R
DS(ON)
, V
GS
@-1.8V, I
D
@-2.5A<50mΩ
Advanced Trench Process Technology
Specially Designed for Switch Load, PWM Application, etc
Lead free in compliance with EU RoHS 2011/65/EU
directive.
Green molding compound as per IEC61249 Std.
(Halogen Free)
Mechanical Data
Case: SC-59 Package
Terminals : Solderable per MIL-STD-750, Method 2026
Marking: A17
Maximum Ratings and Thermal Characteristics
(T
A
=25 C unless otherwise noted)
PARAMETER
Drain-Source Voltage
Gate-Source Voltage
Continuous Drain Current
Pulsed Drain Current
Power Dissipation
T
a
=25
o
C
Derate above 25 C
Operating Junction and Storage Temperature Range
Typical Thermal resistance
-
Junction to Ambient
(Note 3)
R
θJA
100
o
o
o
SYMBOL
V
DS
V
GS
I
D
I
DM
P
D
T
J
,T
STG
LIMIT
UNITS
V
V
A
A
W
mW/ C
o
o
-20
+8
-5.2
-20.8
1.25
10
-55~150
C
C/W
October 22,2015-REV.00
Page 1
PPJA3417
Electrical Characteristics
(T
A
=25 C unless otherwise noted)
PARAMETER
Static
Drain-Source Breakdown Voltage
Gate Threshold Voltage
BV
DSS
V
GS(th)
R
DS(on)
I
DSS
I
GSS
Q
g
Q
gs
Q
gd
Ciss
Coss
Crss
td
(on)
tr
td
(off)
tf
V
GS
=0V, I
D
=-250uA
V
DS
=V
GS
, I
D
=-250uA
V
GS
=-4.5V, I
D
=-5.2A
Drain-Source On-State Resistance
V
GS
=-2.5V, I
D
=-3.7A
V
GS
=-1.8V, I
D
=-2.5A
Zero Gate Voltage Drain Current
Gate-Source Leakage Current
Dynamic
(Note 5)
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Turn-On Delay Time
Turn-On Rise Time
Turn-Off Delay Time
Turn-Off Fall Time
Drain-Source Diode
Maximum Continuous Drain-Source
Diode Forward Current
Diode Forward Voltage
I
S
V
SD
---
I
S
=-1.0A, V
GS
=0V
-
-
-
-0.69
-1.5
-1.2
A
V
V
DS
=-10V, I
D
=-5.2A,
V
GS
=-4.5V
(Note 1,2)
V
DS
=-10V, V
GS
=0V,
f=1.0MHZ
-
-
-
-
-
-
-
-
-
-
18.9
2.8
4.2
1758
153
125
12
68
82
35
-
-
-
-
-
-
-
-
-
-
ns
pF
nC
V
DS
=-20V, V
GS
=0V
V
GS
=+8V, V
DS
=0V
-20
-0.35
-
-
-
-
-
-
-0.59
29
33
40
-0.01
+10
-
-0.9
35
40
50
-1
+100
uA
nA
mΩ
V
V
SYMBOL
TEST CONDITION
MIN.
TYP.
MAX.
UNITS
o
V
DD
=-10V, I
D
=-5.2A,
V
GS
=-4.5V,
R
G
=6Ω
(Note 1,2)
NOTES :
1. Pulse width<300us, Duty cycle<2%
2. Essentially independent of operating temperature typical characteristics.
3. R
JA
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is
defined as the solder mounting surface of the drain pins mounted on a 1 inch FR-4 with 2oz. square pad of copper
4. The maximum current rating is package limited
5. Guaranteed by design, not subject to production testing.
October 22,2015-REV.00
Page 2
PPJA3417
TYPICAL CHARACTERISTIC CURVES
Fig.1 On-Region Characteristics
Fig.2 Transfer Characteristics
Fig.3 On-Resistance vs. Drain Current
Fig.4 On-Resistance vs. Junction temperature
Fig.5 On-Resistance Variation with VGS.
Fig.6 Body Diode Characteristics
October 22,2015-REV.00
Page 3
PPJA3417
TYPICAL CHARACTERISTIC CURVES
Fig.7 Gate-Charge Characteristics
Fig.8 Threshold Voltage Variation with Temperature
Fig.9 Capacitance vs. Drain-Source Voltage.
October 22,2015-REV.00
Page 4
PPJA3417
PART NO PACKING CODE VERSION
Part No Packing Code
PJA3417_R1_00001
Package Type
SC-59
Packing type
3K pcs / 7” reel
Marking
A17
Version
Halogen free
MOUNTING PAD LAYOUT
October 22,2015-REV.00
Page 5
FPGA/CPLD
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