2N7002
60V N-Channel Enhancement Mode MOSFET
FEATURES
• R
DS(ON)
, V
GS
@4.5V,I
DS
@75mA=7.5Ω
• Advanced Trench Process Technology
• High Density Cell Design For Ultra Low On-Resistance
• Specially Designed for Battery Operated Systems, Solid-State Relays
Drivers : Relays, Displays, Lamps, Solenoids, Memories, etc.
• In compliance with EU RoHS 2002/95/EC directives
0.056(1.40)
0.047(1.20)
0.120(3.04)
0.110(2.80)
0.006(0.15)MIN.
• R
DS(ON)
, V
GS
@10V,I
DS
@500mA=5Ω
0.103(2.60)
0.044(1.10)
0.035(0.90)
0.020(0.50)
0.013(0.35)
0.079(2.00)
0.070(1.80)
0.008(0.20)
0.003(0.08)
MECHANICALDATA
• Case: SOT-23 Package
• Terminals : Solderable per MIL-STD-750,Method 2026
• Marking : S72
0.004(0.10)MAX.
Maximum Ratings and Thermal Characteristics (T
A
=25
O
C unless otherwise noted )
PA RA ME TE R
D ra i n-S o urc e Vo lt a g e
G a t e - S o urc e Vo lt a g e
C o nt i nuo us D r a i n C urr e nt
P uls e d D ra i n C urr e nt
1)
S ymb o l
V
DS
V
GS
I
D
I
D M
T
A
= 2 5
O
C
T
A
= 7 5
O
C
P
D
T
J
,T
S TG
R
θJ
A
L i mi t
60
+20
250
1300
350
210
-5 5 to + 1 50
357
0.086(2.20)
Uni t s
V
V
mA
mA
mW
O
M a xi mum P o we r D i s s i p a t i o n
O p e ra t i ng J unc ti o n a nd S t o ra g e Te mp e ra t ur e Ra ng e
Junction-to Ambient Thermal Resistance(PCB mounted)
2
C
O
C /W
Note: 1. Maximum DC current limited by the package
2. Surface mounted on FR4 board, t < 10 sec
PAN JIT RESERVES THE RIGHT TO IMPROVE PRODUCT DESIGN,FUNCTIONS AND RELIABILITY WITHOUT NOTICE
November 01,2010-REV.02
PAGE . 1
2N7002
ELECTRICALCHARACTERISTICS
P a r a me te r
S ta ti c
D ra i n- S o urc e B re a k d o wn Vo lta g e
Ga te Thr e s ho ld Vo lta g e
D ra i n- S o urc e On-S ta te Re s i s ta nc e
D ra i n- S o urc e On-S ta te Re s i s ta nc e
Ze ro Ga te Vo lt a g e D r a i n C urr e nt
Gate Body Leakage
Forward Transconductance
Dynamic
To ta l Ga te C ha r g e
Ga t e -S o ur c e C ha r g e
Ga te -D ra i n C ha r g e
Tur n-On Ti me
Tur n-Off Ti me
Inp ut C a p a c i ta nc e
Outp ut C a p a c i ta nc e
Re ve rs e Tra ns fe r C a p a c i ta nc e
S o ur c e -D r a i n D i o d e
M a x. D i o d e F o rwa r d C ur re nt
D i o d e F o rwa r d Vo lta g e
I
s
V
SD
-
I
S
= 2 5 0 mA , V
G S
= 0 V
-
-
-
0 .9 3
250
1 .2
mA
V
Q
g
Q
gs
Q
gd
t
on
t
o ff
C
i ss
C
oss
C
rs s
V
D S
= 2 5 V, V
G S
= 0 V
f = 1 .0 M H
Z
V
DD
=10V , R
L
=20Ω
I
D
=500mA , V
GEN
=10V
R
G
=10Ω
V
D S
= 1 5 V, I
D
= 5 0 0 m A
V
DD
=4.5V
-
-
-
-
-
-
-
-
0 .6
0 .1
0 .0 8
9
21
-
-
-
0 .7
-
-
15
ns
26
50
25
5
pF
nC
B V
DSS
V
G S ( th)
R
D S ( o n)
R
D S ( o n)
I
D S S
I
G S S
g
fS
V
G S
= 0 V, I
D
= 1 0
μA
V
D S
= V
GS
, I
D
=2 5 0
μ
A
V
GS
=4.5V, I
D
=75mA
V
GS
=10V, I
D
=500mA
V
DS
=60V, V
GS
=0V
V
GS
= +2 0 V, V
D S
= 0 V
V
D S
= 1 5 V, I
D
= 2 5 0 m A
60
1
-
-
-
-
200
-
-
-
-
-
-
-
-
2.5
7 .5
Ω
5
1
+100
-
μA
nA
mS
V
V
S ym b o l
Te s t C o nd i ti o n
M i n.
Typ .
Ma x.
Uni ts
Switching
Test Circuit
V
IN
V
DD
R
L
V
OUT
Gate Charge
Test Circuit
V
GS
V
DD
R
L
R
G
1mA
R
G
November 01,2010-REV.02
PAGE . 2
2N7002
Typical Characteristics Curves (T
A
=25 C,unless otherwise noted)
O
1.2
I
D
-
Drain-to-Source Current
(A)
1.2
V
GS
= 6.0~10V
1
0.8
0.6
0.4
0.2
0
0
5.0V
4.0V
I
D
-
Drain Source Current
(A)
1
0.8
0.6
0.4
0.2
0
0
V
DS
=10V
3.0V
o
T
J
=25 C
1
2
3
4
5
1
2
3
4
5
6
V
DS
-
Drain-to-Source Voltage (V)
V
GS
-
Gate-to-Source Voltage (V)
Fig. 1-TYPICAL FORWARD CHARACTERISTIC
FIG.1- Output Characteristic
5
10
FIG.2- Transfer Characteristic
R
DS(ON)
- On-Resistance
(
W
)
I
D
=500mA
8
6
4
2
o
T
J
=25 C
R
DS(ON)
-
On-Resistance
(
W
)
4
3
2
1
0
V
GS
=10V
V
GS
= 4.5V
T
J
=125
o
C
0
0
0.2
0.4
0.6
0.8
1
1.2
2
3
4
5
6
7
8
9
10
I
D
-
Drain Current (A)
V
GS
- Gate-to-Source Voltage (V)
FIG.3- On Resistance vs Drain Current
R
DS(ON)
- On-Resistance(Normalized)
FIG.4- On Resistance vs Gate to Source Voltage
2
1.8
1.6
1.4
1.2
1
0.8
0.6
V
GS
=10V
I
D
=500mA
0.4
-50
-25
0
25
50
75
100
125
150
T
J
- Junction Temperature (
o
C)
FIG.5- On Resistance vs Junction Temperature
November 01,2010-REV.02
PAGE . 3
2N7002
10
8
6
4
2
0
0
0.2
0.4
0.6
0.8
1
V
GS
- Gate-to-Source Voltage (V)
Vgs
Qg
V
DS=
15V
I
D
=500mA
Vgs(th)
Qg(th)
Qgs
Qsw
Qgd
Qg
Q
g
- Gate Charge (nC)
Fig.6 - Gate Charge Waveform
V
th
- G-S Th r esh o l d Vo l tag e (NORMA L IZED)
Fig.7 - Gate Charge
BV
DSS
- Breakdown Voltage (V)
73
72
71
70
69
68
67
66
65
64
-50
-25
0
25
50
75
100
125
150
1.2
1.1
1
0.9
0.8
0.7
0.6
-50
I
D
=250
m
A
I
D
= 250
m
A
-25
0
25
50
75
100
125
150
T
J
- Junction Temperature (
o
C)
T
J
- Junction Temperature (
o
C)
Fig.8 - Threshold Voltage vs Temperature
10
Fig.9 - Breakdown Voltage vs Junction Temperature
80
70
V
GS
= 0V
C - Capacitance (pF)
f = 1MHz
V
GS
= 0V
I
S
- Source Current (A)
1
60
50
40
30
20
10
Coss
Crss
0
5
10
15
20
25
Ciss
T
J
=25 C
T
J
=125 C
o
o
0.1
T
J
=-55
o
C
0.01
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
0
V
SD
- Source-to-Drain Voltage (V)
V
DS
- Drain-to-Source Voltage (V)
Fig.10 - Source-Drain Diode Forward Voltage
Fig.11 - Capacitance vs Drain to Source Voltage
November 01,2010-REV.02
PAGE . 4
2N7002
MOUNTING PAD LAYOUT
SOT-23
ORDER INFORMATION
• Packing information
T/R - 12K per 13" plastic Reel
T/R - 3K per 7” plastic Reel
LEGAL STATEMENT
Copyright PanJit International, Inc 2011
The information presented in this document is believed to be accurate and reliable. The specifications and information herein are
subject to change without notice. Pan Jit makes no warranty, representation or guarantee regarding the suitability of its produ cts for
any particular purpose. Pan Jit products are not authorized for use in life support devices or systems. Pan Jit does not convey any
license under its patent rights or rights of others.
November 01,2010-REV.02
PAGE . 5
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