MX25V4006E
MX25V4006E
2.5V, 4M-BIT [x 1/x 2]
CMOS SERIAL FLASH MEMORY
Key Features
• 2.35 to 3.6 volt for read, erase, and program operations
• Supports HOLD feature
• Auto Erase and Auto Program Algorithm
• Low Power Consumption
P/N: PM1638
1
REV. 1.8, JUL. 07, 2015
MX25V4006E
Contents
FEATURES .................................................................................................................................................................. 4
GENERAL DESCRIPTION ......................................................................................................................................... 5
PIN CONFIGURATIONS .............................................................................................................................................. 5
PIN DESCRIPTION ...................................................................................................................................................... 5
BLOCK DIAGRAM....................................................................................................................................................... 6
MEMORY ORGANIZATION ......................................................................................................................................... 7
DEVICE OPERATION .................................................................................................................................................. 8
DATA PROTECTION.................................................................................................................................................... 9
HOLD FEATURE........................................................................................................................................................ 10
Table 1. Memory Organization .................................................................................................................................................7
Figure 1. Serial Peripheral Interface Modes Supported ...........................................................................................................8
Table 2. Protected Area Sizes ..................................................................................................................................................9
Figure 2. Hold Condition Operation
............................................................................................................. 10
Table 3. COMMAND DEFINITION .........................................................................................................................................12
COMMAND DESCRIPTION ....................................................................................................................................... 13
POWER-ON STATE ................................................................................................................................................... 26
ELECTRICAL SPECIFICATIONS .............................................................................................................................. 27
(1) Write Enable (WREN) .......................................................................................................................................................13
(2) Write Disable (WRDI) ........................................................................................................................................................13
(3) Read Status Register (RDSR) ..........................................................................................................................................14
(4) Write Status Register (WRSR) ..........................................................................................................................................15
Table 4. Protection Modes ......................................................................................................................................................15
(5) Read Data Bytes (READ) .................................................................................................................................................16
(6) Read Data Bytes at Higher Speed (FAST_READ) ...........................................................................................................16
(7) Dual Output Mode (DREAD) .............................................................................................................................................16
(8) Sector Erase (SE) .............................................................................................................................................................16
(9) Block Erase (BE) ...............................................................................................................................................................17
(10) Chip Erase (CE) ..............................................................................................................................................................17
(11) Page Program (PP) .........................................................................................................................................................17
(12) Deep Power-down (DP) ..................................................................................................................................................18
(13) Release from Deep Power-down (RDP), Read Electronic Signature (RES) .................................................................18
(14) Read Identification (RDID)
..............................................................................................................................................19
(15) Read Electronic Manufacturer ID & Device ID (REMS) ..................................................................................................19
Table 5. ID Definitions
............................................................................................................................................................19
(16) Read SFDP Mode (RDSFDP) .........................................................................................................................................20
Read Serial Flash Discoverable Parameter (RDSFDP) Sequence ........................................................................................20
Table 6. Signature and Parameter Identification Data Values
...............................................................................................21
Table 7. Parameter Table (0): JEDEC Flash Parameter Tables .............................................................................................22
Table 8. Parameter Table (1): Macronix Flash Parameter Tables...........................................................................................24
ABSOLUTE MAXIMUM RATINGS .........................................................................................................................................27
Figure 2. Maximum Negative Overshoot Waveform...............................................................................................................27
CAPACITANCE TA = 25°C, f = 1.0 MHz .................................................................................................................................27
Figure 3. Maximum Positive Overshoot Waveform ................................................................................................................27
Figure 4. INPUT TEST WAVEFORMS AND MEASUREMENT LEVEL
..................................................................................28
Figure 5. OUTPUT LOADING ...............................................................................................................................................28
Table 9. DC CHARACTERISTICS (Temperature = -40°C to 85°C, VCC = 2.35V ~ 3.6V)
...................................................29
Table 10. AC CHARACTERISTICS (Temperature = -40°C to 85°C, VCC = 2.35V ~ 3.6V)
.................................................30
Table 11. Power-Up Timing.....................................................................................................................................................31
P/N: PM1638
2
REV. 1.8, JUL. 07, 2015
MX25V4006E
Timing Analysis ........................................................................................................................................................ 32
Figure 6. Serial Input Timing ..................................................................................................................................................32
Figure 7. Output Timing ..........................................................................................................................................................32
Figure 8. Hold Timing .............................................................................................................................................................33
Figure 9. WP# Disable Setup and Hold Timing during WRSR when SRWD=1 .....................................................................33
Figure 10. Write Enable (WREN) Sequence (Command 06) .................................................................................................34
Figure 11. Write Disable (WRDI) Sequence (Command 04) ..................................................................................................34
Figure 12. Read Status Register (RDSR) Sequence (Command 05) ....................................................................................34
Figure 13. Write Status Register (WRSR) Sequence (Command 01) ...................................................................................35
Figure 14. Read Data Bytes (READ) Sequence (Command 03) ..........................................................................................35
Figure 15. Read at Higher Speed (FAST_READ) Sequence (Command 0B).......................................................................36
Figure 16. Dual Output Read Mode Sequence (Command 3B) .............................................................................................36
Figure 17. Sector Erase (SE) Sequence (Command 20) ......................................................................................................37
Figure 18. Block Erase (BE) Sequence (Command 52 or D8) ..............................................................................................37
Figure 19. Chip Erase (CE) Sequence (Command 60 or C7) ...............................................................................................37
Figure 20. Page Program (PP) Sequence (Command 02) ....................................................................................................38
Figure 21. Deep Power-down (DP) Sequence (Command B9) .............................................................................................38
Figure 22. Read Electronic Signature (RES) Sequence (Command AB) ..............................................................................39
Figure 23. Release from Deep Power-down (RDP) Sequence (Command AB) ...................................................................39
Figure 24. Read Identification (RDID) Sequence (Command 9F)
..........................................................................................40
Figure 25. Read Electronic Manufacturer & Device ID (REMS) Sequence (Command 90) ..................................................40
Figure 26. Power-up Timing ...................................................................................................................................................41
Figure 27. AC Timing at Device Power-Up .............................................................................................................................42
Figure 28. Power-Down Sequence ........................................................................................................................................43
OPERATING CONDITIONS ....................................................................................................................................... 42
ERASE AND PROGRAMMING PERFORMANCE .................................................................................................... 44
DATA RETENTION ................................................................................................................................................... 44
LATCH-UP CHARACTERISTICS .............................................................................................................................. 44
ORDERING INFORMATION ...................................................................................................................................... 45
PART NAME DESCRIPTION ..................................................................................................................................... 46
PACKAGE INFORMATION ........................................................................................................................................ 47
REVISION HISTORY ................................................................................................................................................. 51
8-pin SOP (150mil) .................................................................................................................................................................47
8-land WSON (6x5mm, 0.8mm package height) ....................................................................................................................48
8-LAND USON (2x3mm) ........................................................................................................................................................49
8-pin VSOP (150mil, Max. 0.9mm height)
..............................................................................................................................50
P/N: PM1638
3
REV. 1.8, JUL. 07, 2015
MX25V4006E
4M-BIT [x 1/x 2] CMOS SERIAL FLASH
FEATURES
GENERAL
•
Supports Serial Peripheral Interface -- Mode 0 and
Mode 3
• 4,194,304 x 1 bit structure or 2,097,152 x 2 bits (Dual
Output mode) structure
• 128 Equal Sectors with 4K byte each
- Any Sector can be erased individually
• 8 Equal Blocks with 64K byte each
- Any Block can be erased individually
• Single Power Supply Operation
- 2.35 to 3.6 volt for read, erase, and program opera-
tions
• Latch-up protected to 100mA from -1V to Vcc +1V
PERFORMANCE
• High Performance
- Fast access time: 75MHz serial clock
- Serial clock of Dual Output mode: 70MHz
- Fast program time:
0.6ms(typ.) and 1ms(max.)/page (256-byte per page)
- Byte program time: 9us (typ.)
- Fast erase time:
40ms(typ.)/sector (4K-byte per sector);
0.4s(typ.)/block (64K-byte per block)
• Low Power Consumption
- Low active read current:
12mA(max.) at 75MHz and 4mA(max.) at 33MHz
- Low active programming current: 15mA (typ.)
- Low active sector erase current: 9mA (typ.)
- Low standby current: 15uA (typ.)
- Deep power-down mode 2uA (typ.)
• Minimum 100,000 erase/program cycles
• 20 years data retention
SOFTWARE FEATURES
• Input Data Format
- 1-byte Command code
• Block Lock protection
- The BP0~BP2 status bit defines the size of the area
to be software protected against Program and Erase
instructions
• Auto Erase and Auto Program Algorithm
- Automatically erases and verifies data at selected
sector
- Automatically programs and verifies data at selected
page by an internal algorithm that automatically
times the program pulse widths (Any page to be
programed should have page in the erased state
first)
•
Status Register Feature
•
Electronic Identification
- JEDEC 2-byte Device ID
- RES command, 1-byte Device ID
•
Support Serial Flash Discoverable Parameters (SFDP)
mode
HARDWARE FEATURES
• PACKAGE
-
8-pin SOP (150mil)
- 8-pin VSOP (150mil, Max. 0.9mm height)
- 8-land WSON (6x5mm, 0.8mm package height)
- 8-USON (2x3mm, 0.6mm package height)
-
All devices are RoHS Compliant and Halogen-
free
P/N: PM1638
4
REV. 1.8, JUL. 07, 2015
MX25V4006E
GENERAL DESCRIPTION
The device features a serial peripheral interface and software protocol allowing operation on a simple 4-wire bus.
The four bus signals are a clock input (SCLK), a serial data input (SI), a serial data output (SO), and a chip select (CS#).
Serial access to the device is enabled by CS# input.
When it is in Dual Output read mode, the SI and SO pins become SIO0 and SIO1 pins for data output.
The device provides sequential read operation on the whole chip.
After program/erase command is issued, auto program/erase algorithms which program/erase and verify the speci-
fied page or sector/block locations will be executed. Program command is executed on byte basis, or page basis, or
word basis. Erase command is executed on sector, block, or whole chip basis.
To provide user with ease of interface, a status register is included to indicate the status of the chip. The status read
command can be issued to detect completion status of a program or erase operation via WIP bit.
When the device is not in operation and CS# is high, it is put in standby mode.
The device utilizes Macronix's proprietary memory cell, which reliably stores memory contents even after 100,000
program and erase cycles.
PIN CONFIGURATIONS
8-PIN SOP (150mil)
CS#
SO/SIO1
WP#
GND
1
2
3
4
8
7
6
5
VCC
HOLD#
SCLK
SI/SIO0
PIN DESCRIPTION
SYMBOL DESCRIPTION
CS#
Chip Select
Serial Data Input (for 1 x I/O) / Serial Data
SI/SIO0
Input & Output (for Dual Output mode)
Serial Data Output (for 1 x I/O) / Serial
SO/SIO1
Data Output (for Dual Output mode)
SCLK
Clock Input
WP# Write Protection
Hold, to pause the device without
HOLD#
deselecting the device
VCC
+ 2.5V Power Supply
GND Ground
8-PIN VSOP (150mil, Max. 0.9mm height)
CS#
SO/SIO1
WP#
GND
1
2
3
4
8
7
6
5
VCC
HOLD#
SCLK
SI/SIO0
8-LAND WSON (6x5mm), 8-LAND USON (2x3mm)
CS#
SO/SIO1
WP#
GND
1
2
3
4
8
7
6
5
VCC
HOLD#
SCLK
SI/SIO0
P/N: PM1638
5
REV. 1.8, JUL. 07, 2015
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