MX25L6433F
MX25L6433F
3V, 64M-BIT [x 1/x 2/x 4]
CMOS MXSMIO
®
(SERIAL MULTI I/O)
FLASH MEMORY
Key Features
• Hold Feature
• Multi I/O Support - Single I/O, Dual I/O and Quad I/O
• Auto Erase and Auto Program Algorithms
• Program Suspend/Resume & Erase Suspend/Resume
P/N: PM2130
1
Rev. 1.6, October 21, 2016
MX25L6433F
Contents
1. FEATURES ........................................................................................................................................................ 5
2. GENERAL DESCRIPTION ............................................................................................................................... 6
3. PIN CONFIGURATION ...................................................................................................................................... 7
4. PIN DESCRIPTION ............................................................................................................................................ 7
5. BLOCK DIAGRAM............................................................................................................................................. 8
6. DATA PROTECTION.......................................................................................................................................... 9
Table 1. Protected Area Sizes ..............................................................................................................10
Table 2. 8K-bit Secured OTP Definition
............................................................................................... 11
7. MEMORY ORGANIZATION ............................................................................................................................. 12
Table 3. Memory Organization
.............................................................................................................12
8. DEVICE OPERATION ...................................................................................................................................... 13
9. HOLD FEATURE.............................................................................................................................................. 14
10. COMMAND DESCRIPTION ........................................................................................................................... 15
Table 4. Command Sets
.......................................................................................................................15
10-1. Write Enable (WREN)
..........................................................................................................................18
10-2. Write Disable (WRDI)
...........................................................................................................................19
10-3. Read Identification (RDID)
...................................................................................................................20
10-4. Read Status Register (RDSR)
.............................................................................................................21
10-5. Read Configuration Register (RDCR)
..................................................................................................22
Table 5. Status Register
.......................................................................................................................23
Table 6. Configuration Register
............................................................................................................24
Table 7. Dummy Cycle and Frequency Table
.......................................................................................24
10-6. Write Status Register (WRSR)
.............................................................................................................25
Table 8. Protection Modes
....................................................................................................................26
10-7. Read Data Bytes (READ)
....................................................................................................................28
10-8. Read Data Bytes at Higher Speed (FAST_READ)
..............................................................................29
10-9. Dual Read Mode (DREAD)
..................................................................................................................30
10-10. 2 x I/O Read Mode (2READ)
...............................................................................................................31
10-11. Quad Read Mode (QREAD)
................................................................................................................32
10-12. 4 x I/O Read Mode (4READ)
...............................................................................................................33
10-13. Performance Enhance Mode
...............................................................................................................35
10-14. Burst Read
...........................................................................................................................................36
10-15. Sector Erase (SE)
................................................................................................................................37
10-16. Block Erase (BE)
.................................................................................................................................38
10-17. Block Erase (BE32K)
...........................................................................................................................39
10-18. Chip Erase (CE)
...................................................................................................................................40
10-19. Page Program (PP)
.............................................................................................................................41
10-20. 4 x I/O Page Program (4PP)
................................................................................................................42
10-21. Deep Power-down (DP)
.......................................................................................................................45
10-22. Release from Deep Power-down (RDP), Read Electronic Signature (RES)
.......................................46
10-23. Read Electronic Manufacturer ID & Device ID (REMS)
.......................................................................48
Table 9. ID Definitions
.........................................................................................................................49
10-24. Enter Secured OTP (ENSO)
................................................................................................................49
P/N: PM2130
Rev. 1.6, October 21, 2016
2
MX25L6433F
10-25. Exit Secured OTP (EXSO)
...................................................................................................................49
10-26. Read Security Register (RDSCUR)
.....................................................................................................50
Table 10. Security Register Definition
..................................................................................................51
10-27. Write Security Register (WRSCUR)
.....................................................................................................52
10-28. Program Suspend and Erase Suspend
...............................................................................................53
Table 11. Readable Area of Memory While a Program or Erase Operation is Suspended
..................53
Table 12. Acceptable Commands During Program/Erase Suspend after tPSL/tESL
...........................53
Table 13. Acceptable Commands During Suspend (tPSL/tESL not required)
......................................54
10-29. Program Resume and Erase Resume
.................................................................................................55
10-30. No Operation (NOP)
............................................................................................................................56
10-31. Software Reset (Reset-Enable (RSTEN) and Reset (RST))
...............................................................56
10-32. Read SFDP Mode (RDSFDP)
..............................................................................................................57
Table 14. Signature and Parameter Identification Data Values
...........................................................58
Table 15. Parameter Table (0): JEDEC Flash Parameter Tables
.........................................................59
Table 16. Parameter Table (1): Macronix Flash Parameter Tables
......................................................61
11. POWER-ON STATE ....................................................................................................................................... 63
12. Electrical Specifications
.............................................................................................................................. 64
12-1. Absolute Maximum Ratings
.................................................................................................................64
12-2. Capacitance TA = 25°C, f = 1.0 MHz
...................................................................................................64
Table 17. DC Characteristics
................................................................................................................66
Table 18. AC Characteristics
................................................................................................................67
13. TIMING ANALYSIS ........................................................................................................................................ 69
14. OPERATING CONDITIONS ........................................................................................................................... 71
Table 19. Power-Up/Down Voltage and Timing
....................................................................................73
14-1. Initial Delivery State
.............................................................................................................................73
15. ERASE AND PROGRAMMING PERFORMANCE ........................................................................................ 74
16. DATA RETENTION ........................................................................................................................................ 74
17. LATCH-UP CHARACTERISTICS .................................................................................................................. 74
18. ORDERING INFORMATION .......................................................................................................................... 75
19. PART NAME DESCRIPTION ......................................................................................................................... 76
20. PACKAGE INFORMATION ............................................................................................................................ 77
20-1. 8-pin SOP (200mil)
..............................................................................................................................77
20-2. 16-pin SOP (300mil)
............................................................................................................................78
20-3. 8-WSON (8x6mm)
...............................................................................................................................79
20-4. 8-WSON (6x5mm)
...............................................................................................................................80
20-5. 24 ball TFBGA (6x8mm)
......................................................................................................................81
21. REVISION HISTORY ..................................................................................................................................... 82
P/N: PM2130
3
Rev. 1.6, October 21, 2016
MX25L6433F
Figures
Figure 1. Serial Modes Supported (for Normal Serial mode)
.............................................................. 13
Figure 2. Hold Condition Operation
.................................................................................................... 14
Figure 3. Write Enable (WREN) Sequence (Command 06)
................................................................ 18
Figure 4. Write Disable (WRDI) Sequence (Command 04)
............................................................... 19
Figure 5. Read Identification (RDID) Sequence (Command 9F)
........................................................ 20
Figure 6. Read Status Register (RDSR) Sequence (Command 05)
.................................................. 21
Figure 7. Read
Configuration
Register (RDCR) Sequence
................................................................. 22
Figure 8. Write Status Register (WRSR) Sequence (Command 01)
................................................. 25
Figure 9. WRSR flow
........................................................................................................................... 27
Figure 10. Read Data Bytes (READ) Sequence (Command 03)
....................................................... 28
Figure 11. Read at Higher Speed (FAST_READ) Sequence (Command 0B)
.................................... 29
Figure 12. Dual Read Mode Sequence (Command 3B)
..................................................................... 30
Figure 13. 2 x I/O Read Mode Sequence (Command BB)
.................................................................. 31
Figure 14. Quad Read Mode Sequence (Command 6B)
.................................................................... 32
Figure 15. 4 x I/O Read Mode Sequence (Command EB)
.................................................................. 33
Figure 16. 4 x I/O Read enhance performance Mode Sequence (Command EB) (SPI Mode)
........... 35
Figure 17. Burst Read
......................................................................................................................... 36
Figure 18. Sector Erase (SE) Sequence (Command 20)
................................................................... 37
Figure 19. Block Erase (BE) Sequence (Command D8)
.................................................................... 38
Figure 20. Block Erase 32KB (BE32K) Sequence (Command 52)
................................................... 39
Figure 21. Chip Erase (CE) Sequence (Command 60 or C7)
............................................................ 40
Figure 22. Page Program (PP) Sequence (Command 02)
................................................................ 41
Figure 23. 4 x I/O Page Program (4PP) Sequence (Command 38)
................................................... 42
Figure 24. Program/Erase Flow(1) with read array data
..................................................................... 43
Figure 25. Program/Erase Flow(2) without read array data
................................................................ 44
Figure 26. Deep Power-down (DP) Sequence (Command B9)
......................................................... 45
Figure 27. Read Electronic Signature (RES) Sequence (Command AB)
........................................... 46
Figure 28. Release from Deep Power-down (RDP) Sequence
........................................................... 47
Figure 29. Read Electronic Manufacturer & Device ID (REMS) Sequence
........................................ 48
Figure 30. Read Security Register (RDSCUR) Sequence (Command 2B)
......................................... 50
Figure 31. Write Security Register (WRSCUR) Sequence (Command 2F) (SPI mode)
..................... 52
Figure 32. Suspend to Read Latency
.................................................................................................. 54
Figure 33. Resume to Suspend Latency
............................................................................................. 54
Figure 34. Suspend to Program Latency
............................................................................................ 55
Figure 35. Resume to Read Latency
.................................................................................................. 55
Figure 36. Software Reset Recovery
.................................................................................................. 56
Figure 37. Read Serial Flash Discoverable Parameter (RDSFDP) Sequence
................................... 57
Figure 38. Maximum Negative Overshoot Waveform
......................................................................... 64
Figure 39. Maximum Positive Overshoot Waveform
........................................................................... 64
Figure 40. Input Test Waveforms and Measurement Level
................................................................. 65
Figure 41. Output Loading
.................................................................................................................. 65
Figure 42. Serial Input Timing
............................................................................................................. 69
Figure 43. Output Timing
..................................................................................................................... 69
Figure 44. Hold Timing
........................................................................................................................ 70
Figure 45. WP# Setup Timing and Hold Timing during WRSR when SRWD=1..................................
70
Figure 46. AC Timing at Device Power-Up
.......................................................................................... 71
Figure 47. Power-Down Sequence
..................................................................................................... 72
Figure 48. Power-up Timing
................................................................................................................ 72
Figure 49. Power Up/Down and Voltage Drop
.................................................................................... 73
P/N: PM2130
4
Rev. 1.6, October 21, 2016
MX25L6433F
64M-BIT [x 1 / x 2 / x 4] CMOS MXSMIO
®
(SERIAL MULTI I/O)
FLASH MEMORY
1. FEATURES
GENERAL
• Supports Serial Peripheral Interface -- Mode 0 and
Mode 3
•
67,108,864 x 1 bit structure
or 33,554,432 x 2 bits (two I/O read mode) structure
or 16,777,216 x 4 bits (four I/O mode) structure
• 2048 Equal Sectors with 4K bytes each
- Any Sector can be erased individually
• 256 Equal Blocks with 32K bytes each
- Any Block can be erased individually
• 128 Equal Blocks with 64K bytes each
- Any Block can be erased individually
• Power Supply Operation
- 2.65~3.6 volt for read, erase, and program opera-
tions
• Latch-up protected to 100mA from -1V to Vcc +1V
PERFORMANCE
• High Performance
VCC = 2.65~3.6V
- Normal read
- 50MHz
- Fast read
- FAST_READ, DREAD, QREAD:
133MHz with 8 dummy cycles
- 2READ: 80MHz with 4 dummy cycles,
133MHz with 8 dummy cycles
- 4READ: 80MHz with 6 dummy cycles,
133MHz with 10 dummy cycles
- Configurable dummy cycle number for 2READ
and 4READ operation
- 8/16/32/64 byte Wrap-Around Burst Read Mode
• Low Power Consumption
• Typical 100,000 erase/program cycles
• 20 years data retention
SOFTWARE FEATURES
•
Input Data Format
-
1-byte Command code
•
Advanced Security Features
-
Block lock protection
The BP0-BP3 and T/B status bits define the size
of the area to be protected against program and
erase instructions
•
Additional 8K-bit bit security OTP
- Features unique identifier
- Factory locked identifiable, and customer lockable
•
Auto Erase and Auto Program Algorithms
- Automatically erases and verifies data at selected
sector
- Automatically programs and verifies data at select-
ed page by an internal algorithm that automatically
times the program pulse width (Any page to be
programmed should have page in the erased state
first.)
•
Status Register Feature
•
Command Reset
•
Program/Erase Suspend
•
Program/Erase Resume
•
Electronic Identification
-
JEDEC 1-byte Manufacturer ID and 2-byte Device
ID
- RES command for 1-byte Device ID
•
Support Serial Flash Discoverable Parameters (SFDP)
mode
HARDWARE FEATURES
•
SCLK Input
-
Serial clock input
• SI/SIO0
-
Serial Data Input or Serial Data Input/Output for 2 x
I/O mode or Serial Data Input/Output for 4 x I/O mode
• SO/SIO1
-
Serial Data Output or Serial Data Input/Output for
2 x I/O mode or Serial Data Input/Output for 4 x I/O
mode
• WP#/SIO2
-
Hardware write protection or Serial Data Input/Out-
put for 4 x I/O mode
• HOLD#/SIO3
-
To pause the device without deselecting the device
or serial data Input/Output for 4 x I/O mode
• PACKAGE
- 8-pin SOP (200mil)
- 16-pin SOP (300mil)
- 8-WSON (6x5mm)
- 8-WSON (8x6mm)
- 24 ball TFBGA (6x8mm)
- WLCSP
-
All devices are RoHS Compliant and Halogen-
free
Rev. 1.6, October 21, 2016
P/N: PM2130
5
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