MX25L2006EZUI-12G

MX25L2006E

MX25L2006E

DATASHEET

P/N: PM1578

1

REV.1.5, NOV. 14, 2013

MX25L2006E

Contents

FEATURES ................................................................................................................................................. 4

GENERAL DESCRIPTION ........................................................................................................................ 5

PIN CONFIGURATIONS ............................................................................................................................. 5

PIN DESCRIPTION ..................................................................................................................................... 5

BLOCK DIAGRAM...................................................................................................................................... 6

MEMORY ORGANIZATION ........................................................................................................................ 7

DEVICE OPERATION ................................................................................................................................. 8

DATA PROTECTION................................................................................................................................... 9

HOLD FEATURE....................................................................................................................................... 10

Table 1. Memory Organization ............................................................................................................................. 7

Figure 1. Serial Peripheral Interface Modes Supported ....................................................................................... 8

Table 2. Protected Area Sizes .............................................................................................................................. 9

Figure 2. Hold Condition Operation ................................................................................................................... 10

Table 3. COMMAND DEFINITION ..................................................................................................................... 11

(1) Write Enable (WREN) ................................................................................................................................... 12

(2) Write Disable (WRDI) .................................................................................................................................... 12

(3) Read Status Register (RDSR) ...................................................................................................................... 13

(4) Write Status Register (WRSR) ...................................................................................................................... 14

Table 4. Protection Modes .................................................................................................................................. 14

(5) Read Data Bytes (READ) ............................................................................................................................. 15

(6) Read Data Bytes at Higher Speed (FAST_READ) ....................................................................................... 15

(7) Dual Output Mode (DREAD) ......................................................................................................................... 15

(8) Sector Erase (SE) ......................................................................................................................................... 15

(9) Block Erase (BE)........................................................................................................................................... 16

(10) Chip Erase (CE) .......................................................................................................................................... 16

(11) Page Program (PP) ..................................................................................................................................... 16

(12) Deep Power-down (DP) .............................................................................................................................. 17

(13) Release from Deep Power-down (RDP), Read Electronic Signature (RES) ............................................. 17

(14) Read Identification (RDID)

.......................................................................................................................... 18

(15) Read Electronic Manufacturer ID & Device ID (REMS) .............................................................................. 18

Table 5. ID Definitions

........................................................................................................................................ 18

(16) Read SFDP Mode (RDSFDP)..................................................................................................................... 19

Read Serial Flash Discoverable Parameter (RDSFDP) Sequence .................................................................... 19

Table a.

Signature and Parameter Identification Data Values

........................................................................... 20

Table b. Parameter Table (0): JEDEC Flash Parameter Tables ......................................................................... 21

Table c. Parameter Table (1): Macronix Flash Parameter Tables ....................................................................... 23

COMMAND DESCRIPTION ...................................................................................................................... 12

POWER-ON STATE .................................................................................................................................. 25

ELECTRICAL SPECIFICATIONS ............................................................................................................. 26

ABSOLUTE MAXIMUM RATINGS ..................................................................................................................... 26

P/N: PM1578

2

REV.1.5, NOV. 14, 2013

MX25L2006E

Figure 3.Maximum Negative Overshoot Waveform ........................................................................................... 26

CAPACITANCE TA = 25°C, f = 1.0 MHz............................................................................................................. 26

Figure 4. Maximum Positive Overshoot Waveform ............................................................................................ 26

Figure 5. INPUT TEST WAVEFORMS AND MEASUREMENT LEVEL

.............................................................. 27

Figure 6. OUTPUT LOADING ........................................................................................................................... 27

Table 6. DC CHARACTERISTICS (Temperature = -40°C to 85°C, VCC = 2.7V ~ 3.6V)

................................. 28

Table 7. AC CHARACTERISTICS (Temperature = -40°C to 85°C, VCC = 2.7V ~ 3.6V)

................................. 29

Table 8. Power-Up Timing .................................................................................................................................. 30

Timing Analysis ....................................................................................................................................... 31

Figure 7. Serial Input Timing .............................................................................................................................. 31

Figure 8. Output Timing ...................................................................................................................................... 31

Figure 9. Hold Timing ......................................................................................................................................... 32

Figure 10. WP# Disable Setup and Hold Timing during WRSR when SRWD=1 ............................................... 32

Figure 11. Write Enable (WREN) Sequence (Command 06) ............................................................................. 33

Figure 12. Write Disable (WRDI) Sequence (Command 04).............................................................................. 33

Figure 13. Read Status Register (RDSR) Sequence (Command 05) ................................................................ 33

Figure 14. Write Status Register (WRSR) Sequence (Command 01)............................................................... 34

Figure 15. Read Data Bytes (READ) Sequence (Command 03) ...................................................................... 34

Figure 16. Read at Higher Speed (FAST_READ) Sequence (Command 0B)................................................... 35

Figure 17. Dual Output Read Mode Sequence (Command 3B) ......................................................................... 35

Figure 18. Sector Erase (SE) Sequence (Command 20) .................................................................................. 36

Figure 19. Block Erase (BE) Sequence (Command 52 or D8) .......................................................................... 36

Figure 20. Chip Erase (CE) Sequence (Command 60 or C7) ........................................................................... 36

Figure 21. Page Program (PP) Sequence (Command 02)................................................................................ 37

Figure 22. Deep Power-down (DP) Sequence (Command B9)......................................................................... 37

Figure 23. Read Electronic Signature (RES) Sequence (Command AB) .......................................................... 38

Figure 24. Release from Deep Power-down (RDP) Sequence (Command AB) ............................................... 38

Figure 25. Read Identification (RDID) Sequence (Command 9F)

...................................................................... 39

Figure 26. Read Electronic Manufacturer & Device ID (REMS) Sequence (Command 90).............................. 39

Figure 27. Power-up Timing ............................................................................................................................... 40

OPERATING CONDITIONS ...................................................................................................................... 41

Figure 28. AC Timing at Device Power-Up ......................................................................................................... 41

Figure 29. Power-Down Sequence .................................................................................................................... 42

ERASE AND PROGRAMMING PERFORMANCE ................................................................................... 43

DATA RETENTION .................................................................................................................................. 43

LATCH-UP CHARACTERISTICS ............................................................................................................. 43

ORDERING INFORMATION ..................................................................................................................... 44

PART NAME DESCRIPTION .................................................................................................................... 45

PACKAGE INFORMATION ....................................................................................................................... 46

REVISION HISTORY ................................................................................................................................ 49

P/N: PM1578

3

REV.1.5, NOV. 14, 2013

MX25L2006E

FEATURES

2M-BIT [x 1/x 2] CMOS SERIAL FLASH

GENERAL

• Serial Peripheral Interface compatible -- Mode 0 and Mode 3

• 2,097,152 x 1 bit structure or 1,048,576 x 2 bits (Dual Output mode) structure

• 64 Equal Sectors with 4K byte each

- Any Sector can be erased individually

• 4 Equal Blocks with 64K byte each

- Any Block can be erased individually

• Single Power Supply Operation

- 2.7 to 3.6 volt for read, erase, and program operations

• Latch-up protected to 100mA from -1V to Vcc +1V

PERFORMANCE

• High Performance

- Fast access time: 86MHz serial clock

- Serial clock of Dual Output mode: 80MHz

- Fast program time: 0.6ms(typ.) and 3ms(max.)/page

- Byte program time: 9us (typ.)

- Fast erase time: 40ms(typ.)/sector (4K-byte per sector) ; 0.4s(typ.)/block (64K-byte per block)

• Low Power Consumption

- Low active read current: 12mA(max.) at 86MHz and 4mA(max.) at 33MHz

- Low active programming current: 15mA (typ.)

- Low active sector erase current: 9mA (typ.)

- Low standby current: 15uA (typ.)

- Deep power-down mode 2uA (typ.)

• Minimum 100,000 erase/program cycles

• 20 years data retention

SOFTWARE FEATURES

• Input Data Format

- 1-byte Command code

• Block Lock protection

- The BP0~BP1 status bit defines the size of the area to be software protected against Program and Erase in-

structions

• Auto Erase and Auto Program Algorithm

-

Automatically erases and verifies data at selected sector

-

Automatically programs and verifies data at selected page by an internal algorithm that automatically times the

program pulse widths (Any page to be programed should have page in the erased state first)

•

Status Register Feature

•

Electronic Identification

-

JEDEC 2-byte Device ID

- RES command, 1-byte Device ID

•

Support Serial Flash Discoverable Parameters (SFDP) mode

HARDWARE FEATURES

• PACKAGE

-

8-pin SOP (150mil)

- 8-land WSON (6x5mm, 0.8mm package height)

- 8-land USON (2x3x0.6mm)

-

All devices are RoHS Compliant and Halogen-free

P/N: PM1578

REV.1.5, NOV. 14, 2013

4

MX25L2006E

GENERAL DESCRIPTION

The device features a serial peripheral interface and software protocol allowing operation on a simple 3-wire bus.

The four bus signals are a clock input (SCLK), a serial data input (SI), a serial data output (SO), and a chip select (CS#).

Serial access to the device is enabled by CS# input.

When it is in Dual Output read mode, the SI and SO pins become SIO0 and SIO1 pins for data output.

The device provides sequential read operation on whole chip.

After program/erase command is issued, auto program/erase algorithms which program/erase and verify the speci-

fied page or sector/block locations will be executed. Program command is executed on byte basis, or page basis, or

word basis for erase command is executes on sector, or block, or whole chip basis.

To provide user with ease of interface, a status register is included to indicate the status of the chip. The status read

command can be issued to detect completion status of a program or erase operation via WIP bit.

When the device is not in operation and CS# is high, it is put in standby mode.

The device utilizes Macronix's proprietary memory cell, which reliably stores memory contents even after 100,000

program and erase cycles.

PIN CONFIGURATIONS

8-PIN SOP (150mil)

CS#

SO/SIO1

WP#

GND

1

2

3

4

8

7

6

5

VCC

HOLD#

SCLK

SI/SIO0

PIN DESCRIPTION

SYMBOL DESCRIPTION

CS#

Chip Select

Serial Data Input (for 1 x I/O) / Serial Data

SI/SIO0

Input & Output (for Dual Output mode)

Serial Data Output (for 1 x I/O) / Serial

SO/SIO1

Data Output (for Dual Output mode)

SCLK

Clock Input

WP# Write Protection

Hold, to pause the device without

HOLD#

deselecting the device

VCC

+ 3.3V Power Supply

GND Ground

8-LAND, WSON (6x5mm)

CS#

SO/SIO1

WP#

GND

1

2

3

4

8

7

6

5

VCC

HOLD#

SCLK

SI/SIO0

8-LAND USON (2x3mm)

CS#

SO/SIO1

WP#

GND

1

2

3

4

8

7

6

5

VCC

HOLD#

SCLK

SI/SIO0

P/N: PM1578

5

REV.1.5, NOV. 14, 2013