产品描述存储器构架(格式):FLASH 存储器接口类型:SPI - Dual/Quad I/O, QPI 存储器容量:256Mb (256M x 1, 128M x 2, 64M x 4) 存储器类型:Non-Volatile 256-Mbit(256M x 1/128M x 2/64M x 4),工作电压:3V
存储器构架(格式):FLASH 存储器接口类型:SPI - Dual/Quad I/O, QPI 存储器容量:256Mb (256M x 1, 128M x 2, 64M x 4) 存储器类型:Non-Volatile 256-Mbit(256M x 1/128M x 2/64M x 4),工作电压:3V
• Protocol Support - Single I/O, Dual I/O and Quad I/O
• Support DTR (Double Transfer Rate) Mode
• Support clock frequency up to 133MHz
MX25L25645G
Contents
1. FEATURES .............................................................................................................................................................. 5
2. GENERAL DESCRIPTION ..................................................................................................................................... 6
6. DATA PROTECTION................................................................................................................................................ 9
Table 2. Protected Area Sizes ...................................................................................................................10
Table 7. Status Register ............................................................................................................................34
4 x I/O Read Mode (4READ) ................................................................................................................... 47
9-10.
9-11.
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9-15.
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9-18.
P/N: PM2075
2
Rev. 1.6, November 07, 2017
MX25L25645G
4 x I/O Double Transfer Rate Read Mode (4DTRD) ................................................................................ 49
Preamble Bit ........................................................................................................................................... 51
4 Byte Address Command Set ................................................................................................................. 55
9-39. Program Suspend .................................................................................................................................... 82
11. POWER-ON STATE ........................................................................................................................................... 101
14. ERASE AND PROGRAMMING PERFORMANCE ............................................................................................ 110
15. ERASE AND PROGRAMMING PERFORMANCE (Factory Mode) ................................................................ 110
16. DATA RETENTION ............................................................................................................................................ 111
18. ORDERING INFORMATION .............................................................................................................................. 112
19. PART NAME DESCRIPTION ............................................................................................................................. 113
20. PACKAGE INFORMATION ................................................................................................................................ 114
21. REVISION HISTORY ......................................................................................................................................... 120
P/N: PM2075
4
Rev. 1.6, November 07, 2017
MX25L25645G
3V 256M-BIT [x 1/x 2/x 4] CMOS MXSMIO
®
(SERIAL MULTI I/O)
FLASH MEMORY
1. FEATURES
GENERAL
•
•
Supports Serial Peripheral Interface -- Mode 0 and
Mode 3
Single Power Supply Operation
- 2.7 to 3.6 volt for read, erase, and program opera-
tions
268,435,456 x 1 bit structure
or 134,217,728 x 2 bits (two I/O mode) structure
or 67,108,864 x 4 bits (four I/O mode) structure
Protocol Support
- Single I/O, Dual I/O and Quad I/O
Latch-up protected to 100mA from -1V to Vcc +1V
Low Vcc write inhibit is from 1.5V to 2.5V
Fast read for SPI mode
- Support clock frequency up to 133MHz for all
protocols
- Support Fast Read, 2READ, DREAD, 4READ,
QREAD instructions
- Support DTR (Double Transfer Rate) Mode
- Configurable dummy cycle number for fast read
operation
Quad Peripheral Interface (QPI) available
Equal Sectors with 4K byte each,
or Equal Blocks with 32K byte each
or Equal Blocks with 64K byte each
- Any Block can be erased individually
Programming :
- 256byte page buffer
- Quad Input/Output page program(4PP) to enhance
program performance
Typical 100,000 erase/program cycles
20 years data retention
•
Additional 4K bit security OTP
-
Features unique identifier
-
Factory locked identifiable, and customer lock-
able
Command Reset
Program/Erase Suspend and Resume operation
Electronic Identification
-
JEDEC 1-byte manufacturer ID and 2-byte de-
vice ID
- RES command for 1-byte Device ID
- REMS command for 1-byte manufacturer ID and
1-byte device ID
Support Serial Flash Discoverable Parameters
(SFDP) mode
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SOFTWARE FEATURES
• Input Data Format
- 1-byte Command code
• Advanced Security Features
- Block lock protection
The BP0-BP3 and T/B status bits define the size of
the area to be protected against program and erase
instructions
- Individual sector protection function (Solid Protect)
HARDWARE FEATURES
•
SCLK Input
- Serial clock input
• SI/SIO0
- Serial Data Input or Serial Data Input/Output for