ME2805
Ultra-small package High-precision Voltage Detector with delay
circuit, ME2805 Series
General Description
ME2805 Series
is a series of high-precision
voltage detectors with a built-in delay time generator
of fixed time developed using CMOS process.
Internal oscillator and counter timer can delay the
release signal without external parts. Detect voltage
is extremely accurate with minimal temperature drift.
CMOS output configurations are available.
Features
Highly accuracy： ±
1%
Low power consumption：TYP 0.9uA (V
DD
=3V)
Detect
voltage
range
：
1.0V~6.5V
in
0.1V
increments
Operating voltage range：0.7V~7V
Detect voltage temperature characteristics：
TYP±
100ppm/℃
Output configuration： CMOS
Typical Application
Power monitor for portable equipment such
as notebook computers, digital still cameras,
PDA, and cellular phones
Constant voltage power monitor for cameras,
video
devices.
Power monitor for microcomputers and reset
for CPUs.
System battery life and charge voltage
monitors
equipment
and
communication
Package
● 3-pin SOT23-3、SOT23
Typical Application Circuit
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Page 1 of 11
ME2805
Selection Guide
ME 2805X X X X X G
Environment mark
Package:
M3-SOT23-3
X-SOT23
Output Voltage
Function
Product Type
Product Series
Microne
product series
ME2805A263M3G
ME2805A263XG
ME2805A293M3G
ME2805A293XG
ME2805A308XG
ME2805A463XG
product description
V
OUT
=2.63V；Rising edge detection；Package：SOT23-3
V
OUT
=2.63V；Rising edge detection；Package：SOT23
V
OUT
=2.93V；Rising edge detection；Package：SOT23-3
V
OUT
=2.93V；Rising edge detection；Package：SOT23
V
OUT
=3.08V；Rising edge detection；Package：SOT23
V
OUT
=4.63V；Rising edge detection；Package：SOT23
NOTE:
If you need other voltage and package, please contact our sales staff.
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Page 2 of 11
ME2805
Pin Configuration
1
3
3
2
1
2
SOT-23
SOT-23-3
Pin Assignment
PIN Number
SOT-23-3/SOT-23
1
2
3
Pin Name
VSS
VOUT
VDD
Function
Ground
Output Voltage
Input Voltage
Block Diagram
Absolute Maximum Ratings
PARAMETER
V
IN
Input Voltage
Output Current
Output Voltage
Continuous Total Power
Dissipation
CMOS
SOT-23-3
SOT-23
SYMBAL
V
IN
I
OUT
V
OUT
Pd
T
Opr
T
stg
T
solder
MM
HBM
RATINGS
8
50
GND-0.3~V
IN
+0.3
300
250
-40~+85
-40~+125
260℃, 10s
400
4000
V
V
UNITS
V
mA
V
mW
℃
℃
Operating Ambient Temperature
Storage Temperature
Soldering temperature and time
ESD
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Page 3 of 11
ME2805
Electrical Characteristics
(-V
DET
(S)=1.0V to 6.5V± ,Ta=25
O
C , unless otherwise noted)
2%
Parameter
Detect Voltage
(Output Voltage)
Hysteresis
Range
Symbol
-VDET
VHYS
Conditions
-
-
VDD=3V (below 2.5V)
Min
.
-VDET（S）
×0.99
0.03
-
-
-
0.01
Typ
-VDET(S)
0.06
0.9
1.4
1.8
0.19
Max.
-VDET(S)
×1.01
0.1
1.5
2.8
3.6
--
Units
V
Test
circuit
1
V
Supply Current
ISS
VDD=5V (2.5V-4.5V)
VDD=7V (4.5V-6.5V)
uA
2
Iout
N-ch
Output Current
VDS=0.5V VDD=0.7V
mA
3
Iout
P-ch
VDS=0.5V VDD=7V
1.7
3.4
--
mA
V
ms
us
ppm/℃
4
Operating
voltage
Delay time
Temperature
characteristics
VDD
Td1
Td2
VDET
Ta
VDET
-
VDD=-VDET+1V DS low
VDD=-VDET+1V DS high
0.7
130
110
-
-
200
220
±
100
7
290
330
±
350
1
1
5
1
Ta
=-40℃ ~ 85℃
Note： 1、-VDET(S)
：Specified
Detection Voltage value
2、-VDET
：Actual
Detection Voltage value
3、Release Voltage：+VDET=-VDET+VHYS
Test Circuits:
1.
2.
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Page 4 of 11
ME2805
3.
4.
5.
Functional Description：
1.
Basic Operation: CMOS Output (Active Low)
1-1. When the power supply voltage (VDD) is higher than the release voltage (+VDET), the Nch transistor is OFF and
the Pch transistor is ON to provide VDD (high) at the output. Since the Nch transistor N1 in Figure 1 is OFF, the
(
R
B
R
C
)
VDD
R
A
R
B
R
C
.
comparator input voltage is
1-2. When the VDD goes below +VDET, the output provides the VDD level, as long as VDD remains above the
detection voltage (–VDET). When the VDD falls below –VDET (point A in Figure 2), the Nch transistor
becomes ON, the Pch transistor becomes OFF, and the VSS level appears at the output. At this time the Nch
R
B
VDD
R
R
B
.
transistor N1 in Figure 1 becomes ON, the comparator input voltage is changed to
A
1-3. When the VDD falls below the minimum operating voltage, the output becomes undefined, or goes to VDD when
the output is pulled up to VDD.
1-4. The VSS level appears when VDD rises above the minimum operating voltage. The VSS level still appears
even when VDD surpasses the –VDET, as long as it does not exceed the release voltage +VDET.
1-5. When VDD rises above +VDET (point B in Figure 2), the Nch transistor becomes OFF and the Pch transistor
becomes ON to provide VDD at the output. The VDD at the OUT pin is delayed for Td due to the delay circuit.
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Page 5 of 11
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