FM25F005
512K-BIT SERIAL FLASH MEMORY
Datasheet
Oct. 2016
FM25F005 512K-BIT SERIAL FLASH MEMORY
Ver. 1.4
Datasheet
1
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FM25F005 512K-BIT SERIAL FLASH MEMORY
Ver. 1.4
Datasheet
2
1. Description
The FM25F005 is a 512K-bit (64K-byte) Serial Flash
memory,
with
advanced
write
protection
mechanisms. The FM25F005 supports the standard
Serial Peripheral Interface (SPI), and a high
performance Dual output as well as Dual I/O.
The FM25F005 can be programmed 1 to 256 bytes
at a time, using the Page Program instruction. It is
designed to allow either single Sector/Block at a
time or full chip erase operation. The FM25F005
can be configured to protect part of the memory as
the software protected mode. The device can
sustain a minimum of 100K program/erase cycles on
each sector or block.
High Reliability
– Endurance: 100,000 program/erase cycles
– Data retention: 20 years
Green Package
– 8-pin SOP (150mil)
– 8-pin TSSOP
– 8-pin TDFN (2x3mm)
– All Packages are RoHS Compliant and Halogen-
free
3. Packaging Type
SOP 8 (150mil)
CS#
DO(DQ
1
)
WP#
VSS
1
2
3
4
8
7
6
5
VCC
HOLD#
CLK
DI(DQ
0
)
2. Features
512Kbit of Flash memory
– 16 uniform sectors with 4K-byte each
– 1 block with 64K-byte
– 2 uniform blocks with 32K-byte each
– 256 bytes per programmable page
Wide Operation Range
– 2.3V~3.6V single voltage supply
– Industrial temperature range
Serial Interface
– Standard SPI: CLK, CS#, DI, DO, WP#
– Dual SPI: CLK, CS#, DQ
0
, DQ
1
, WP#
– Continuous READ mode support
High Performance
– Max FAST_READ clock frequency: 100MHz
– Max READ clock frequency: 50MHz
– Typical page program time: 1.5ms
– Typical sector erase time: 90ms
– Typical chip erase time: 0.5s
Low Power Consumption
– Typical standby current: 1µA
Security
– Software and hardware write protection
– Lockable 256-Byte OTP security sectors
– Low Voltage Write Inhibit
– 64-Bit Unique ID for each device
TSSOP8
CS#
DO(DQ
1
)
WP#
VSS
1
2
3
4
8
7
6
5
VCC
HOLD#
CLK
DI(DQ
0
)
TDFN8 (2x3mm)
CS#
DO(DQ
1
)
WP#
VSS
1
2
3
4
8 VCC
7 HOLD#
6 CLK
5 DI(DQ
0
)
4. Pin Configurations
PIN PIN
I/O
FUNCTION
NO. NAME
1
CS#
I Chip Select Input
DO
Data Output (Data Input Output
2
I/O
(1)
(DQ
1
)
1)
3
WP#
I Write Protect Input
4
VSS
Ground
DI
Data Input (Data Input Output
5
I/O
(1)
(DQ
0
)
0)
6
CLK
I Serial Clock Input
7 HOLD# I Hold Input
8
VCC
Power Supply
Note:
1 DQ
0
and DQ
1
are used for Dual SPI instructions.
FM25F005 512K-BIT SERIAL FLASH MEMORY
Ver. 1.4
Datasheet
3
5.
Block Diagram
Figure 1 FM25F005 Serial Flash Memory Block Diagram
FM25F005 512K-BIT SERIAL FLASH MEMORY
Ver. 1.4
Datasheet
4
6.
Pin Descriptions
Serial Clock (CLK):
The SPI Serial Clock Input (CLK) pin provides the timing for serial input and
output operations.
Serial Data Input, Output and I/Os (DI, DO and DQ
0
, DQ
1
):
The FM25F005 supports standard
SPI and Dual SPI operation. Standard SPI instructions use the unidirectional DI (input) pin to
serially write instructions, addresses or data to the device on the rising edge of the Serial Clock
(CLK) input pin. Standard SPI also uses the unidirectional DO (output) to read data or status
from the device on the falling edge of CLK.
Dual SPI instructions use the bidirectional DQ pins to serially write instructions, addresses or
data to the device on the rising edge of CLK and read data or status from the device on the
falling edge of CLK.
Chip Select (CS#):
The SPI Chip Select (CS#) pin enables and disables device operation.
When CS# is high, the device is deselected and the Serial Data Output (DO, or DQ
0
, DQ
1
) pins
are at high impedance. When deselected, the devices power consumption will be at standby
levels unless an internal erase, program or write status register cycle is in progress. When CS#
is brought low, the device will be selected, power consumption will increase to active levels and
instructions can be written to and data read from the device. After power-up, CS# must transition
from high to low before a new instruction will be accepted. The CS# input must track the VCC
supply level at power-up (see “9 Write Protection” and Figure 25). If needed a pull-up resister on
CS# can be used to accomplish this.
HOLD (HOLD#):
The HOLD# pin allows the device to be paused while it is actively selected.
When HOLD# is brought low, while CS# is low, the DO pin will be at high impedance and signals
on the DI and CLK pins will be ignored (don’t care). When HOLD# is brought high, device
operation can resume. The HOLD# function can be useful when multiple devices are sharing the
same SPI signals. The HOLD# pin is active low.
Write Protect (WP#):
The Write Protect (WP#) pin can be used to prevent the Status Registers
from being written. Used in conjunction with the Status Register’s Block Protect (BP2, BP1 and
BP0) bits and Status Register Protect (SRP) bits, a portion as small as a 4KB sector or the entire
memory array can be hardware protected. The WP# pin is active low.
FM25F005 512K-BIT SERIAL FLASH MEMORY
Ver. 1.4
Datasheet
5
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