FM25Q04
4M-BIT SERIAL FLASH MEMORY
Datasheet
Oct. 2015
FM25Q04 4M-BIT SERIAL FLASH MEMORY
Ver. 0.1
Datasheet
1
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FM25Q04 4M-BIT SERIAL FLASH MEMORY
Ver. 0.1
Datasheet
2
1. Description
The FM25Q04 is a 4M-bit (512K-byte) Serial Flash
memory,
with
advanced
write
protection
mechanisms. The FM25Q04 supports the standard
Serial Peripheral Interface (SPI), Dual/Quad I/O as
well as 2-clock instruction cycle Quad Peripheral
Interface (QPI). They are ideal for code shadowing to
RAM, executing code directly from Dual/Quad SPI
(XIP) and storing voice, text and data.
The FM25Q04 can be programmed 1 to 256 bytes
at a time, using the Page Program instruction. It is
designed to allow either single Sector/Block at a
time or full chip erase operation. The FM25Q04
can be configured to protect part of the memory as
the software protected mode. The device can
sustain a minimum of 100K program/erase cycles on
each sector or block.
High Reliability
– Endurance: 100,000 program/erase cycles
– Data retention: 20 years
Green Package
– 8-pin SOP (150mil)
– 8-pin SOP (208mil)
– 8-pin TSSOP8
– 8-pin TDFN (2×3mm)
– All Packages are RoHS Compliant and Halogen-
free
Note
1.This feature is available upon special order.
Please contact
Shanghai Fudan Microelectronics Group
Co., Ltd
for details.
3. Packaging Type
2. Features
4Mbit of Flash memory
– 128 uniform sectors with 4K-byte each
– 8 uniform blocks with 64K-byte each
– 16 uniform blocks with 32K-byte each
– 256 bytes per programmable page
Wide Operation Range
– 2.3V~3.6V single voltage supply
– Industrial temperature range
Serial Interface
– Standard SPI: CLK, CS#, DI, DO, WP#
– Dual SPI: CLK, CS#, DQ
0
, DQ
1
, WP#
– Quad SPI: CLK, CS#, DQ
0
, DQ
1
, DQ
2
, DQ
3
– QPI: CLK, CS#, DQ
0
, DQ
1
, DQ
2
, DQ
3
– Continuous READ mode support
– Allow true XIP (execute in place) operation
High Performance
– Max FAST_READ clock frequency: 104MHz
– Dual I/O Data transfer up to 208Mbits/s
– Quad I/O I/O Data transfer up to 416Mbits/s
– Typical page program time: 1.5ms
– Typical sector erase time: 80ms
– Typical block erase time: 120/150ms
– Typical chip erase time: 1.2s
Low Power Consumption
– Typical standby current: 1μA
Security
– Software and hardware write protection
– Lockable 2X512-Byte OTP security sectors
– 64-Bit Unique ID for each device
(1)
– Discoverable Parameters (SFDP) Register
4. Pin Configurations
PIN PIN
I/O
FUNCTION
NO. NAME
1
CS#
I Chip Select Input
DO
Data Output (Data Input Output
2
I/O
(1)
(DQ
1
)
1)
WP#
Write Protect Input (Data Input
3
I/O
Output 2)
(2)
(DQ
2
)
4
VSS
Ground
DI
Data Input (Data Input Output
5
I/O
(1)
(DQ
0
)
0)
6
CLK
I Serial Clock Input
HOLD#
Hold Input (Data Input Output
7
I/O
(2)
(DQ
3
)
3)
8
VCC
Power Supply
Note:
1 DQ
0
and DQ
1
are used for Dual SPI instructions.
2 DQ
0
– DQ
3
are used for Quad SPI and QPI instructions.
FM25Q04 4M-BIT SERIAL FLASH MEMORY
Ver. 0.1
Datasheet
3
5.
Block Diagram
Figure 1 FM25Q04 Serial Flash Memory Block Diagram
FM25Q04 4M-BIT SERIAL FLASH MEMORY
Ver. 0.1
Datasheet
4
6.
Pin Descriptions
Serial Clock (CLK):
The SPI Serial Clock Input (CLK) pin provides the timing for serial input and
output operations.
Serial Data Input, Output and I/Os (DI, DO and DQ
0
, DQ
1
, DQ
2
, DQ
3
):
The FM25Q04 supports
standard SPI, Dual SPI, Quad SPI and QPI operation. Standard SPI instructions use the
unidirectional DI (input) pin to serially write instructions, addresses or data to the device on the
rising edge of the Serial Clock (CLK) input pin. Standard SPI also uses the unidirectional DO
(output) to read data or status from the device on the falling edge of CLK.
Dual/Quad SPI and QPI instructions use the bidirectional DQ pins to serially write instructions,
addresses or data to the device on the rising edge of CLK and read data or status from the
device on the falling edge of CLK. Quad SPI and QPI instructions require the non-volatile Quad
Enable bit (QE) in Status Register-2 to be set. When QE=1, the WP# pin becomes DQ
2
and
HOLD# pin becomes DQ
3
.
Chip Select (CS#):
The SPI Chip Select (CS#) pin enables and disables device operation.
When CS# is high, the device is deselected and the Serial Data Output (DO, or DQ
0
, DQ
1
, DQ
2
,
DQ
3
) pins are at high impedance. When deselected, the devices power consumption will be at
standby levels unless an internal erase, program or write status register cycle is in progress.
When CS# is brought low, the device will be selected, power consumption will increase to active
levels and instructions can be written to and data read from the device. After power-up, CS#
must transition from high to low before a new instruction will be accepted. The CS# input must
track the VCC supply level at power-up (see “9 Write
Protection”
and Figure 72). If needed a pull-
up resister on CS# can be used to accomplish this.
HOLD (HOLD#):
The HOLD# pin allows the device to be paused while it is actively selected.
When HOLD# is brought low, while CS# is low, the DO pin will be at high impedance and signals
on the DI and CLK pins will be ignored (don’t care). When HOLD# is brought high, device
operation can resume. The HOLD# function can be useful when multiple devices are sharing the
same SPI signals. The HOLD# pin is active low. When the QE bit of Status Register-2 is set for
Quad I/O, the HOLD# pin function is not available since this pin is used for DQ
3
.
Write Protect (WP#):
The Write Protect (WP#) pin can be used to prevent the Status Registers
from being written. Used in conjunction with the Status Register’s Block Protect (CMP, TB, BP2,
BP1 and BP0) bits and Status Register Protect (SRP) bits, a portion as small as a 4KB sector or
the entire memory array can be hardware protected. The WP# pin is active low. However, when
the QE bit of Status Register-2 is set for Quad I/O, the WP# pin function is not available since
this pin is used for DQ
2
.
FM25Q04 4M-BIT SERIAL FLASH MEMORY
Ver. 0.1
Datasheet
5
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