FIR4N60LG
Advanced N-Ch Power MOSFET
PIN Connection TO-252(D-PAK)
General Description
FIR4N60LG is an N-channel enhancement mode power
MOS field effect transistor which is produced using Silan
proprietary
F-Cell
TM
structure
VDMOS
technology.
The
1
3
improved planar stripe cell and the improved guard ring
terminal have been especially tailored to minimize on-state
resistance, provide superior switching performance, and
withstand high energy pulse in the avalanche and commutation
mode.
These devices are widely used in AC-DC power suppliers, DC
DC converters and H-bridge PWM motor drivers.
-
2
1
3
Features
•
•
•
•
•
4A,600V,R
DS(on)
（
typ
）
=2.0
Ω@V
GS
=10V
Low gate charge
Low Crss
Fast switching
Improved dv/dt capability
YAWW
Marking Diagram
FIR4N60L
Y
A
WW
= Year
= Assembly Location
= Work Week
FIR4N60L
= Specific Device Code
Absolute Maximum Ratings (Ta = 25
o
C
unless otherwise noted; reference only
)
Characteristics
Drain-Source Voltage
Gate-Source Voltage
Drain Current
Drain Current Pulsed
Power Dissipation(T
C
=25°C)
-Derate above 25°C
Single Pulsed Avalanche Energy(Note
1)
Operation Junction Temperature Range
Storage Temperature Range
T
C
=25°C
T
C
=100°C
Symbol
V
DS
V
GS
I
D
I
DM
P
D
Ratings
600
±30
4.0
2.5
16
77
0.62
217
-55½+150
-55½+150
Unit
V
V
A
A
W
W/°C
mJ
°C
°C
E
AS
T
J
T
stg
@ 2014 Copyright By American First Semiconductor
Page 1/6
FIR4N60LG
Thermal Characteristics
Characteristics
Thermal Resistance, Junction-to-Case
Thermal Resistance, Junction-to-Ambient
Symbol
R
θJC
R
θJA
Ratings
1.61
110
Unit
°C/W
°C/W
Electrical Characteristics (Ta = 25
o
C
unless otherwise noted; reference only
)
Characteristics
Drain -Source Breakdown Voltage
Symbol
B
VDSS
Test conditions
25
°
C,
V
GS
=0V, I
D
=250µA
125
°
C,
V
GS
=0V, I
D
=250µA
25
°
C,
V
DS
=800V, V
GS
=0V
125
°
C,
V
DS
=800V, V
GS
=0V
150
°
C,
V
DS
=800V, V
GS
=0V
Min.
600
600
--
--
--
--
2.0
--
--
--
--
--
--
--
Typ.
--
--
--
--
--
--
--
2.0
509.00
57.57
2.59
14.20
27.73
34.67
28.53
11.88
3.33
4.90
Max.
--
--
10
50
100
Unit
V
V
uA
uA
uA
Drain-Source Leakage Current
I
DSS
Gate-Source Leakage Current
Gate Threshold Voltage
Static Drain- Source On State
Resistance
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Turn-on Delay Time
Turn-on Rise Time
Turn-off Delay Time
Turn-off Fall Time
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
I
GSS
V
GS(th)
R
DS(on)
C
iss
C
oss
C
rss
t
d(on)
t
r
t
d(off)
t
f
Q
g
Q
gs
Q
gd
V
GS
=±30V, V
DS
=0V
V
GS
= V
DS
, I
D
=250µA
V
GS
=10V, I
D
=2A
±100
4.0
2.4
--
--
--
--
--
--
--
--
--
--
nA
V
Ω
V
DS
=25V,V
GS
=0V,
f=1.0MHZ
V
DD
=300V,I
D
=4A,
R
G
=25Ω
(Note2,3)
V
DS
=480V,I
D
=4A,
V
GS
=10V
(Note 2,3)
pF
ns
--
--
--
--
nC
Source-Drain Diode Ratings And Characteristics
Characteristics
Continuous Source Current
Pulsed Source Current
Diode Forward Voltage
Reverse Recovery Time
Reverse Recovery Charge
Notes:
1.
2.
3.
L=30mH, I
AS
=3.45A, V
DD
=100V, R
G
=25Ω, starting T
J
=25°C;
Pulse Test: Pulse width ≤300μs,Duty cycle≤2%;
Essentially independent of operating temperature.
Symbol
I
S
I
SM
V
SD
T
rr
Q
rr
Test conditions
Integral Reverse P-N
Junction Diode in the
MOSFET
I
S
=4.0A,V
GS
=0V
I
S
=4.0A,V
GS
=0V,
dI
F
/dt=100A/µs (Note 2)
Min.
--
--
--
--
--
Typ.
--
--
--
408
1.98
Max.
4.0
16
1.4
--
--
A
V
ns
µC
Unit
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Page 2/6
FIR4N60LG
Typical Characteristics
Figure 1. On-Region Characteristics
10
Variable
V
GS
=4.5V
V
GS
=5V
V
GS
=5.5V
V
GS
=6V
V
GS
=7V
V
GS
=8V
Figure 2. Transfer Characteristics
100
-55°C
25°C
150°C
Drain Current
–
I
D
(A)
Drain Current
–
I
D
(A)
10
1
V
GS
=10V
V
GS
=15V
1
Notes:
1.250µS pulse test
2.V
DS
=50V
Notes:
1.250µS pulse test
2.T
C
=25°C
0.1
0.1
1
10
100
0.1
0
1
2
3
4
5
6
7
8
9 10
Drain-Source Voltage
–
V
DS
(V)
Figure 3. On-Resitance Variation vs.
Drain Current and Gate Voltage
Gate-Source Voltage– V
GS
(V)
Figure 4. Body Diode Forward Voltage
Variation vs. Source Current and Temperature
100
Drain-Source On-Resistance
–
R
DSON)
(Ω)
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
V
GS
=10V
V
GS
=20V
Reverse Drain Current
–
I
DR
(A)
-55°C
25°C
150°C
10
Notes:
1.250µS pulse test
2.V
GS
=0V
1
Note: T
J
=25°C
2
4
6
8
0.1
0.2
0.4
0.6
0.8
1.0
1.2
1.4
Drain Current
–
I
D
(A)
Source-Drain Voltage– V
SD
(V)
Figure 5. Capacitance Characteristics
1000
Gate-Source Voltage– V
GS
(V)
Figure 6. Gate Charge Characteristics
12
V
DS
=480V
V
DS
=300V
V
DS
=120V
900
800
Capasistance(pF)
C
iss
=C
gs
+C
gd
(C
ds
=shorted)
C
oss
=C
ds
+C
gd
C
rss
=C
gd
10
8
6
4
2
700
600
500
400
300
200
100
0
0.1
1
10
100
C
iss
C
oss
C
rss
Notes:
1. V
GS
=0V
2. f=1MHz
Note: I
D
=4.0A
0
0
2
4
6
8
10
12
14
Drain-Source Voltage
–
V
DS
(V)
Total Gate Charge
–
Q
g
(nC)
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Page 3/6
FIR4N60LG
Typical Characteristics(Continued)
1.2
Drain-Source Breakdown
Voltage(Normalized)
–
B
VDSS
Figure 7. Breakdown Voltage Variation
vs. Temperature
Drain-Source On-Resistance
(Normalized)
–
R
DS(ON)
3.0
2.5
2.0
1.5
1.0
0.5
0.0
-100
Figure 8. On-resistance Variation
vs. Temperature
1.1
1.0
0.9
Notes:
1. V
GS
=0V
2. I
D
=250µA
Notes:
1. V
GS
=10V
2. I
D
=2.0A
0.8
-100
-50
0
50
100
150
200
-50
0
50
100
150
200
Junction Temperature
–
T
J
(°C)
Junction Temperature
–
T
J
(°C)
10
2
Figure 9. Max. Safe Operating
Area(FIR4N60LG)
Operation in This Area is
Limited by R
DS(ON)
4
Figure 10. Maximum Drain Current vs.
Case Temperature
Drain Current - I
D
(A)
100µs
1ms
10ms
10
0
Drain Current - I
D
(A)
10
3
10
1
3
DC
2
10
-1
Notes:
1.T
C
=25°C
2.T
j
=150°C
3.Single Pulse
1
10
-2
10
0
10
1
10
2
0
25
50
75
100
125
150
Case Temperature
–
T
C
(°C)
Drain Source Voltage - V
DS
(V)
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Page 4/6
FIR4N60LG
Typical Test Circuit
Gate Charge Test Circuit & Waveform
50KΩ
12V
200nF
300nF
Same Type
as DUT
V
GS
10V
Qg
V
DS
Qgs
Qgd
V
GS
DUT
3mA
Charge
Resistive Switching Test Circuit & Waveform
V
DS
V
GS
R
L
V
DD
V
DS
90%
R
G
DUT
10V
td(on)
V
GS
10%
tr
t
on
td(off)
t
f
t
off
Unclamped Inductive Switching Test Circuit & Waveform
L
E
AS
=
V
DS
I
D
R
G
DUT
10V
tp
B
VDSS
1
2
2
LI
AS
B
VDSS
-
V
DD
B
VDSS
I
AS
V
DD
V
DD
I
D(t)
V
DS(t)
tp
Time
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Page 5/6
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