ESMT
SDRAM
M12L64164A (2Y)
1M x 16 Bit x 4 Banks
Synchronous DRAM
FEATURES
JEDEC standard 3.3V power supply
LVTTL compatible with multiplexed address
Four banks operation
MRS cycle with address key programs
- CAS Latency (2 & 3)
- Burst Length (1, 2, 4, 8 & full page)
- Burst Type (Sequential & Interleave)
All inputs are sampled at the positive going edge of the
system clock
DQM for masking
Auto & self refresh
64ms refresh period (4K cycle)
- 15.6
μ
s refresh interval
ORDERING INFORMATION
Product ID
M12L64164A-5TG2Y
M12L64164A-6TG2Y
M12L64164A-7TG2Y
M12L64164A-5BG2Y
M12L64164A-6BG2Y
M12L64164A-7BG2Y
Max Freq.
200MHz
166MHz
143MHz
200MHz
166MHz
143MHz
Package
54 TSOP II
54 TSOP II
54 TSOP II
54 VBGA
54 VBGA
54 VBGA
Comments
Pb-free
Pb-free
Pb-free
Pb-free
Pb-free
Pb-free
GENERAL DESCRIPTION
The M12L64164A is 67,108,864 bits synchronous high data rate Dynamic RAM organized as 4 x 1,048,576 words by
16 bits. Synchronous design allows precise cycle controls with the use of system clock I/O transactions are possible on
every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same
device to be useful for a variety of high bandwidth, high performance memory system applications.
PIN CONFIGURATION (TOP VIEW)
(TSOPII 54L, 400milX875mil Body, 0.8mm Pin Pitch)
BALL CONFIGURATION (TOP VIEW)
(BGA54, 8mmX8mmX1mm Body, 0.8mm Ball Pitch)
V
DD
D Q0
V
D DQ
D Q1
D Q2
V
S SQ
D Q3
D Q4
V
D D Q
D Q5
D Q6
V
S SQ
DQ 7
V
DD
LD QM
WE
C AS
R AS
CS
BA0
BA1
A
1 0
/AP
A
0
A
1
A
2
A
3
V
DD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
V
SS
DQ15
V
S SQ
DQ14
DQ13
V
DDQ
DQ12
DQ11
V
S SQ
DQ10
DQ9
V
DDQ
DQ8
V
SS
NC
U DQ M
CLK
CKE
NC
A
11
A
9
A
8
A
7
A
6
A
5
A
4
V
SS
1
A
VSS
2
DQ15
3
VSSQ
4
5
6
7
VDDQ
8
DQ0
9
VDD
B
DQ14
DQ13
VDDQ
VSSQ
DQ2
DQ1
C
DQ12
DQ11
VSSQ
VDDQ
DQ4
DQ3
D
DQ10
DQ9
VDDQ
VSSQ
DQ6
DQ5
E
DQ8
NC
VSS
VDD
LDQM
DQ7
F
UDQM
CLK
CKE
CAS
RAS
WE
G
NC
A11
A9
BA0
BA1
CS
H
A8
A7
A6
A0
A1
A10
J
VSS
A5
A4
A3
A2
VDD
Elite Semiconductor Memory Technology Inc.
Publication Date: May 2012
Revision: 1.1
1/45
ESMT
FUNCTIONAL BLOCK DIAGRAM
CLK
CKE
Address
Mode
Register
Clock
Generator
Bank D
Bank C
Bank B
Row
Address
Buffer
&
Refresh
Counter
Row Decoder
M12L64164A (2Y)
Bank A
Sense Amplifier
Command Decoder
Control Logic
CS
RAS
CAS
WE
Data Control Circuit
Input & Output
Buffer
Latch Circuit
Column
Address
Buffer
&
Refresh
Counter
L(U)DQM
Column Decoder
DQ
PIN FUNCTION DESCRIPTION
PIN
CLK
CS
CKE
A0 ~ A11
BA1 , BA0
NAME
System Clock
Chip Select
Clock Enable
Address
Bank Select Address
INPUT FUNCTION
Active on the positive going edge to sample all inputs
Disables or enables device operation by masking or enabling all
inputs except CLK , CKE and L(U)DQM
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior new command.
Disable input buffers for power down in standby.
Row / column address are multiplexed on the same pins.
Row address : RA0~RA11, column address : CA0~CA7
Selects bank to be activated during row address latch time.
Selects bank for read / write during column address latch time.
Latches row addresses on the positive going edge of the CLK with
RAS
Row Address Strobe
RAS low.
Enables row access & precharge.
Latches column address on the positive going edge of the CLK with
CAS
Column Address Strobe
CAS low.
Enables column access.
Enables write operation and row precharge.
Latches data in starting from CAS ,
WE
active.
Makes data output Hi-Z, t
SHZ
after the clock and masks the output.
Blocks data input when L(U)DQM active.
Data inputs / outputs are multiplexed on the same pins.
Power and ground for the input buffers and the core logic.
Isolated power supply and ground for the output buffers to provide
improved noise immunity.
This pin is recommended to be left No Connection on the device.
WE
Write Enable
Data Input / Output Mask
Data Input / Output
Power Supply / Ground
Data Output Power / Ground
No Connection
L(U)DQM
DQ0 ~ DQ15
VDD / VSS
VDDQ / VSSQ
NC
Elite Semiconductor Memory Technology Inc.
Publication Date: May 2012
Revision: 1.1
2/45
ESMT
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Voltage on any pin relative to V
SS
Voltage on V
DD
supply relative to V
SS
Operating ambient temperature
Storage temperature
Power dissipation
Short circuit current
Note:
SYMBOL
V
IN
, V
OUT
V
DD
, V
DDQ
T
A
T
STG
P
D
I
OS
VALUE
-1.0 ~ 4.6
-1.0 ~ 4.6
0 ~ +70
-55 ~ +150
1
50
M12L64164A (2Y)
UNIT
V
V
°
C
°
C
W
mA
Permanent device damage may occur if ABSOLUTE MAXIMUM RATING are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC OPERATING CONDITION
Recommended operating conditions (Voltage referenced to VSS = 0V)
PARAMETER
Supply voltage
Input logic high voltage
Input logic low voltage
Output logic high voltage
Output logic low voltage
Input leakage current
Output leakage current
Note:
SYMBOL
V
DD
, V
DDQ
V
IH
V
IL
V
OH
V
OL
I
IL
I
OL
MIN
3.0
2.0
-0.3
2.4
-
-5
-5
TYP
3.3
3.0
0
-
-
-
-
MAX
3.6
V
DD
+0.3
0.8
-
0.4
5
5
UNIT
V
V
V
V
V
1
2
I
OH
= -2mA
I
OL
= 2mA
3
4
NOTE
μ
A
μ
A
1. V
IH
(max) = 4.6V AC for pulse width
≤
10ns acceptable.
2. V
IL
(min) = -1.5V AC for pulse width
≤
10ns acceptable.
3. Any input 0V
≤
V
IN
≤
V
DD
, all other pins are not under test = 0V.
4. D
out
is disabled, 0V
≤
V
OUT
≤
V
DD
.
CAPACITANCE
(V
DD
= 3.3V, T
A
= 25
°
C , f = 1MHz)
PARAMETER
Input capacitance (A0 ~ A11, BA0 ~ BA1)
Input capacitance
(CLK, CKE, CS , RAS , CAS ,
WE
&
L(U)DQM)
Data input/output capacitance (DQ0 ~ DQ15)
C
IN2
C
OUT
2
2
4
6
pF
pF
SYMBOL
C
IN1
MIN
2
MAX
4
UNIT
pF
Elite Semiconductor Memory Technology Inc.
Publication Date: May 2012
Revision: 1.1
3/45
ESMT
DC CHARACTERISTICS
Recommended operating condition unless otherwise noted
PARAMETER
Operating Current
(One Bank Active)
SYMBOL
TEST CONDITION
Burst Length = 1, t
RC
≥
t
RC
(min), I
OL
= 0 mA,
t
CC
= t
CC
(min)
CKE
≤
V
IL
(max), t
CC
= t
CC
(min)
CKE & CLK
≤
V
IL
(max), t
CC
=
∞
CKE
≥
V
IH
(min), CS
≥
V
IH
(min), t
CC
= t
CC
(min)
Input signals are changed one time during 2CLK
CKE
≥
V
IH
(min), CLK
≤
V
IL
(max), t
CC
=
∞
input signals are stable
CKE
≤
V
IL
(max), t
CC
= t
CC
(min)
CKE & CLK
≤
V
IL
(max), t
CC
=
∞
CKE
≥
V
IH
(min), CS
≥
V
IH
(min), t
CC
=15ns
Active Standby Current
in non power-down mode
(One Bank Active)
I
CC3N
I
CC3NS
Operating Current
(Burst Mode)
Refresh Current
Self Refresh Current
Note:
I
CC4
I
CC5
I
CC6
Input signals are changed one time during 2clks
All other pins
≥
V
DD
-0.2V or
≤
0.2V
CKE
≥
V
IH
(min), CLK
≤
V
IL
(max), t
CC
=
∞
input signals are stable
I
OL
= 0 mA, Page Burst, All Bank active
Burst Length = 4, CAS Latency = 3
t
RFC
≥
t
RFC
(min), t
CC
= t
CC
(min)
CKE
≤
0.2V
M12L64164A (2Y)
VERSION
-5
60
-6
50
2
1
20
-7
40
UNIT
NOTE
I
CC1
mA
1,2
I
CC2P
Precharge Standby Current
in power-down mode
I
CC2PS
I
CC2N
Precharge Standby Current
in non power-down mode
Active Standby Current
in power-down mode
I
CC2NS
I
CC3P
I
CC3PS
mA
mA
10
8
8
mA
30
mA
25
80
65
70
55
1
60
45
mA
mA
mA
mA
1,2
1. Measured with outputs open.
2. Input signals are changed one time during 2 CLKS.
Elite Semiconductor Memory Technology Inc.
Publication Date: May 2012
Revision: 1.1
4/45
ESMT
AC OPERATING TEST CONDITIONS
(V
DD
= 3.3V
±
0.3V)
PARAMETER
Input levels (Vih/Vil)
Input timing measurement reference level
Input rise and fall-time
Output timing measurement reference level
Output load condition
3.3V
1200
Ω
Output
870
Ω
50pF
V
OH
(DC) =2.4V , I
OH
= -2 mA
V
OL
(DC) =0.4V , I
OL
= 2 mA
Output
M12L64164A (2Y)
VALUE
2.4/0.4
1.4
tr/tf = 1/1
1.4
See Fig. 2
Vtt = 1.4V
50
Ω
Z0 =50
Ω
50pF
UNIT
V
V
ns
V
(Fig. 1) DC Output Load Circuit
(Fig. 2) AC Output Load Circuit
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
PARAMETER
Row active to row active delay
RAS to CAS delay
Row precharge time
Row active time
@ Operating
Row cycle time
@ Auto refresh
Last data in to col. address delay
Last data in to row precharge
Last data in to burst stop
Col. address to col. address delay
Refresh period (4,096 rows)
Number of valid
Output data
SYMBOL
t
RRD
(min)
t
RCD
(min)
t
RP
(min)
t
RAS
(min)
t
RAS
(max)
t
RC
(min)
t
RFC
(min)
t
CDL
(min)
t
RDL
(min)
t
BDL
(min)
t
CCD
(min)
t
REF
(max)
53
55
VERSION
-5
10
15
15
38
-6
12
18
18
40
100
58
60
1
2
1
1
64
2
1
63
70
-7
14
21
21
42
UNIT
ns
ns
ns
ns
us
ns
ns
CLK
CLK
CLK
CLK
ms
ea
1
1,5
2
2
2
3
6
4
NOTE
1
1
1
1
CAS latency = 3
CAS latency = 2
Note:
1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then
rounding off to the next higher integer.
2. Minimum delay is required to complete with.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
5. A new command may be given t
RFC
after self refresh exit.
6. A maximum of eight consecutive AUTO REFRESH commands (with t
RFC
(min)) can be posted to any given SDRAM, and
the maximum absolute interval between any AUTO REFRESH command and the next AUTO REFRESH command is
8x15.6
μ
s.
Elite Semiconductor Memory Technology Inc.
Publication Date: May 2012
Revision: 1.1
5/45
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