BL24C02P
I²C-Compatible Serial EEPROM
General Description
The BL24C02P is 2-Kbit I²C-compatible Serial EEPROM (Electrically Erasable Programmable Memory)
device. It contains a memory array of 256
×
8bits, which is organized in 8 bytes per page. BL24C02P
provides the following devices for different application.
Device Selection Table
Device Name
BL24C02P
Voltage Range
1.7V~5.5V
Temp. Range
-40°C ~ 85°C
Max. Clock Frequency
1MHz[1]
Note 1: 400 kHz for VCC < 2.5V
Features
Single Supply Voltage and High Speed
–
–
–
Sequential & Random Read Features
Page Write Modes, Partial Page Writes Allowed
Write protect of the whole memory array
Self-timed Write Cycle (5ms maximum)
High Reliability
–
–
Minimum operating voltage down to 1.5V
1 MHz clock from 2.5V to 5.5V
400kHz clock from 1.7V to 2.5V
Read current 0.6mA, maximum
Write current 2.0mA, maximum
Low power CMOS technology
–
–
Endurance: > 1 Million Write Cycles
Data Retention: > 100 Years
Schmitt Trigger, Filtered Inputs for Noise
Suppression
Latch-up Capability: +/- 200mA
Package: PDIP, SOP, TSSOP, DFN, TSOT23-5
1. Pin Configuration
８-lead
PDIP
８-lead
SOP
８-lead
TSSOP
８-pad
DFN
5-lead TSOT23-5
WP
VCC
５ A0
６ A1
７ A2
８ GND
１
２
３
５
４
A0
A1
A2
GND
１
２
３
４
５
６
７
８
VCC
WP
SCL
SDA
A0
A1
A2
GND
１
２
３
４
５
６
７
８
VCC
WP
SCL
SDA
A0
A1
A2
GND
１
２
３
４
５
６
７
８
VCC
WP
SCL
SDA
VCC １
WP
２
SCL ３
SDA ４
Bottem view
SCL
GND
SDA
Pin Definition
Pin
1
2
3
4
5
6
7
8
Name
A0
A1
A2
GND
SDA
SCL
WP
VCC
Type
I/O
Input
Input
Ground
I/O
Input
Input
Power
Table 1-1 Pin Definition
BL24C02P 2Kbits (256×8) Belling Proprietary Information. Unauthorized Photocopy and Duplication Prohibited
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Description
Slave Address Setting
Slave Address Setting
Slave Address Setting
Ground
Serial Data Input and Serial Data Output
Serial Clock Input
Write Protect, Low Enable Write
Power
BL24C02P 2Kbits (256×8)
Pin Descriptions
Serial Clock (SCL):
The SCL input is used to positive-edge clock data in and negative-edge clock data out
of each device.
Serial Data (SDA):
The SDA pin is bidirectional for serial data transfer. This pin is open drain driven and
may be wire-Ored with any number of other open-drain or open-collector devices.
Device Addresses (A2, A1, A0):
The A2, A1 and A0 pins are device address inputs. Typically, the A2, A1 and
A0 pins are for hardware addressing and a total of 8 devices can be connected on a single bus system.
If these pins are left floating, the A2, A1 and A0 pins will be internally pulled down to GND.
Write PROTECT (WP):
The Write Protect input, when WP is connected directly to VCC, all write operations
to the memory are inhibited. When connected to GND, allows normal write operations. If the pin is left
floating, the WP pin will be internally pulled down to GND.
2. Block Diagram
SCL
SDA
Start Stop Control
Logic
EN
High Voltage Generator
Serial Bus
Control Logic
WCB
Write Control
Logic
Page Data Latch
MATCH
I
N
C
L
O
A
D
X -DECODER
NC
E1
E2
Slave Address
Comparator
EEPROM ARRAY
Address Counter
DataOut/ACK
Serial MUX
V
CC
GND
Y-DECODER
Figure 2-1 Block Diagram
3. ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Storage Temperature .......................-65°C to +150°C
Operation Temperature ....................-40°C to +85°C
Maximum Operation Voltage............. 6.25V
Voltage on Any Pin with Respect to Ground .....................-1.0V to (Vcc+1.0)V
DC Output Current ............................5.0mA
2-16
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BL24C02P 2Kbits (256×8) Belling Proprietary Information. Unauthorized Photocopy and Duplication Prohibited
BL24C02P 2Kbits (256×8)
NOTICE:
Stresses above those listed under “Absolute Maximum Ratings” may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at those or any
other conditions above those indicated in the operational listings of this specification is not implied.
Exposure to maximum rating conditions for extended periods may affect device reliability.
Table 3-1 Pin Capacitance [1]
Symbol
C
I/O
C
IN
Parameter
Input / Output Capacitance (SDA)
Input Capacitance (A0, A1,A2,WP,SCL)
Max.
8
6
Units
pF
pF
Test Condition
V
I/O
=GND
V
IN
=GND
Note: [1] Test Conditions: TA = 25° F = 1MHz, Vcc = 5.0V
C,
Table 3-2 DC Characteristics（Unless otherwise specified, VCC = 1.7V to 5.5V, TA = –40° to 85°
C
C）
Symbol
V
CC
Isb
I
CC1
I
CC2
I
LI
I
LO
V
IL
V
IH
V
OL1
V
OL2
Parameter
Supply Voltage
Standby Current
Supply Current
Supply Current
Input Leakage Current
Output Leakage Current
Input Low Level
Input High Level
Output Low Level
V
CC
= 1.7V (SDA)
Output Low Level
V
CC
= 3.0V (SDA)
Min.
1.7
-
-
-
-
-
-
–0.6
0.7V
CC
-
-
Typ.
-
-
-
0.3
1.0
0.10
0.05
-
-
-
-
Max.
5.5
1.0
3.0
0.6
1.6
1.0
1.0
0.3V
CC
V
CC
+0.5
0.2
0.4
Unit
V
uA
uA
mA
mA
µA
µA
V
V
V
V
I
OL
= 1.5mA
I
OL
= 2.1mA
Test Condition
BL24C02P
Vcc = 3.3V, T
A
= 85°C
Vcc = 5.5V, T
A
= 85°C
Vcc=5.5V,
Read at 400Khz
Vcc=5.5V
Write at 400Khz
V
IN
= V
CC
or GND
V
OUT
= V
CC
or GND
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BL24C02P 2Kbits (256×8)
Table 3-3 AC Characteristics
(Unless otherwise specified, VCC=1.7V to 5.5V, TA=- 40° to 85° CL=100pF, Test Conditions are listed in
C
C,
Notes [2])
Symbol
f
SCL
t
LOW
t
HIGH
t
AA
t
I
t
BUF
t
HD.STA
t
SU.STA
t
HD.DAT
t
SU.DAT
t
R
t
F
t
SU.STO
t
DH
t
SU.WP
t
HD.WP
t
WR
Parameter
Clock Frequency, SCL
Clock Pulse Width Low
Clock Pulse Width High
Clock Low to Data Out Valid
Noise Suppression Time
Time the bus must be free before a
new transmission can start
Start Hold Time
Start Setup Time
Data In Hold Time
Data In Setup Time
Inputs Rise Time
[1]
Inputs Fall Time
[1]
Stop Setup Time
Data Out Hold Time
WP pin Setup Time
WP pin Hold Time
Write Cycle Time
1.7≤V
CC
<2.5
Min.
-
1.3
0.6
0.05
-
1.3
0.6
0.6
0
0.1
-
-
0.6
0.05
1.2
1.2
-
Typ.
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Max.
400
-
-
0.9
0.1
-
-
-
-
-
0.3
0.3
-
-
-
-
5
Min.
-
0.4
0.4
0.05
-
0.5
0.25
0.25
0
0.1
-
-
0.25
0.05
0.6
0.6
-
2.5≤V
CC
≤5.5
Typ.
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Max.
1000
-
-
0.55
0.05
-
-
-
-
-
0.3
0.1
-
-
-
-
5
Units
kHz
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
ms
Notes: [1] This parameter is ensured by characterization not 100% tested
[2] AC measurement conditions:
RL (connects to VCC): 1.3k (2.5V, 5.5V), 10k (1.7V)
Input pulse voltages: 0.3 VCC to 0.7 VCC
Input rise and fall times: ≤50ns
Input and output timing reference voltages: 0.5VCC
Table 3-4 Reliability Characteristic [1]
Symbol
EDR
[2]
DRET
Parameter
Endurance
Data Retention
Min.
1,000,000
100
Typ.
Max.
Unit
Write cycles
Years
Note: [1] This parameter is ensured by characterization and is not 100% tested
[2] Under the condition: 25° 3.3V, Page mode
C,
BL24C02P 2Kbits (256×8) Belling Proprietary Information. Unauthorized Photocopy and Duplication Prohibited
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BL24C02P 2Kbits (256×8)
Figure 3-1 Bus Timing
t
R
t
F
t
HIGH
t
LOW
SCL
t
SU.STA
t
HD.STA
SDA(IN)
t
HD.DAT
t
SU.DAT
t
SU.STO
t
AA
SDA(OUT)
t
DH
t
BUF
t
SU.WCB
t
HD.WCB
WCB
Figure 3-2 Write Cycle Timing
SCL
SDA
D0
ACK
STOP Conditon
t
WR
START Conditon
Note: [1] The write cycle time tWR is the time from a valid stop condition of a write sequence to the end of the
internal clear/write cycle.
4. Device Operation
4.1 Data Input
The SDA pin is normally pulled high with an external device. Data on the SDA pin may change only
during SCL low time periods (see to Figure 4-1). Data changes during SCL high periods will indicate a
start or stop condition as defined below.
Figure 4-1 Data Validity
SCL
SDA
Data Stable
Data Change
Data Stable
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