BL24C02A/04A/08A/16A
Features
Compatible with all I
2
C bidirectional data
transfer protocol
Memory array:
–
–
–
Page Write within 3 ms
Partial Page Writes Allowed
Write Protect Pin for Hardware Data Protection
Schmitt Trigger, Filtered Inputs for Noise
Suppression
High-reliability
–
–
2K bits (256X 8) / 4K bits (512 X 8) / 8K
bits (1024 X 8) / 16K bits (2048 X 8) of
EEPROM
–
Page size: 16 bytes
1 MHz
Endurance: 1 Million Write Cycles
Data Retention: 100 Years
HBM 8000V
Single supply voltage and high speed:
–
Enhanced ESD/Latch-up protection
–
Random and sequential Read modes
Write:
–
TSOT23-5、8-lead PDIP/SOP/TSSOP and UDFN
packages
Byte Write within 3 ms
Description
The BL24C02A/BL24C04A/BL24C08A/BL24C16A
provides 2048/4096/8192/16384 bits of serial
electrically erasable and programmable read-
only memory (EEPROM), organized as
256/512/1024/2048 words of 8 bits each.
The device is optimized for use in many
industrial and commercial applications where
low-power
essential.
and
low-voltage
operation
are
Pin Configuration
８-lead
PDIP
８-lead
SOP
８-lead
TSSOP
８-pad
DFN
5-lead TSOT23-5
WP
VCC
1
NC
2
NC
3
NC
4
GND
１
２
３
５
４
NC
NC
NC
GND
１
２
３
４
8
7
6
5
VCC
WP
SCL
SDA
NC
NC
NC
GND
１
２
３
４
8
7
6
5
VCC
WP
SCL
SDA
NC
NC
NC
GND
１
２
３
４
8
7
6
5
VCC
WP
SCL
SDA
VCC
WP
8
7
SCL
6
SDA
5
Bottem view
SCL
GND
SDA
BL24C02A/04A/08A/16A Belling Proprietary Information. Unauthorized Photocopy and Duplication Prohibited
© 2016 Belling All Rights Reserved www.belling.com.cn
1-16
BL24C02A/04A/08A/16A
Pin Descriptions
Pin Name
SDA
SCL
WP
GND
Vcc
Type
I/O
I
I
P
P
Functions
Serial Data
Serial Clock Input
Write Protect
Ground
Power Supply
Table 1
Block Diagram
Vcc
GND
WP
SCL
SDA
START STOP
LOGIC
EN
SERIAL CONTROL
LOGIC
LOAD
CCMP
DEVICE ADDRESS
COMPARATOR
DATA RECOVERY
HIGH VOLTAGE
PUMP/TIMING
LOAD
INC
X DECODER
DATA WORD
ADRESS COUNTER
EEPROM
Y DECODER
SERIAL MUX
DIN
DOUT/ACKNOWLEDGE
DOUT
Figure 1
SERIAL DATA (SDA):
The SDA pin is bi-directional for serial data transfer. This pin is open-drain driven
and may be wire-ORed with any number of other open-drain or open- collector devices.
SERIAL CLOCK (SCL):
The SCL input is used to positive edge clock data into each EEPROM device
and negative edge clock data out of each device.
BL24C02A/04A/08A/16A Belling Proprietary Information. Unauthorized Photocopy and Duplication Prohibited
© 2016 Belling All Rights Reserved www.belling.com.cn
2-16
BL24C02A/04A/08A/16A
WRITE PROTECT (WP):
The BL24C02A/BL24C04A/BL24C08A/BL24C16A has a Write Protect pin that
provides hardware data protection. The Write Protect pin allows normal read/write operations when
connected to ground (GND). When the Write Protection pin is connected to Vcc, the write protection
feature is enabled and operates as shown in the following
Table 2.
WP Pin Status
At VCC
At GND
Table 2
BL24C02A/04A/08A/16A
Full Array
Normal Read/Write Operations
Functional Description
1.
Memory Organization
BL24C02A, 2K SERIAL EEPROM:
Internally organized with 16 pages of 16 bytes each, the 2K requires an 8-
bit data word address for random word addressing.
BL24C04A, 4K SERIAL EEPROM:
Internally organized with 32 pages of 16 bytes each, the 4K requires a 9-
bit data word address for random word addressing.
BL24C08A, 8K SERIAL EEPROM:
Internally organized with 64 pages of 16 bytes each, the 8K requires a 10-
bit data word address for random word addressing.
BL24C16A, 16K SERIAL EEPROM:
Internally organized with 128 pages of 16 bytes each, the 16K requires an
11-bit data word address for random word addressing.
2.
Device Operation
CLOCK and DATA TRANSITIONS:
The SDA pin is normally pulled high with an external device. Data on the
SDA pin may change only during SCL low time periods (see
Figure 2).
Data changes during SCL high
periods will indicate a start or stop condition as defined below.
START CONDITION:
A high-to-low transition of SDA with SCL high is a start condition which must
precede any other command (see
Figure 3).
STOP CONDITION:
A low-to-high transition of SDA with SCL high is a stop condition. After a read
sequence, the stop command will place the EEPROM in a standby power mode (see
Figure 3).
ACKNOWLEDGE:
All addresses and data words are serially transmitted to and from the EEPROM in 8-bit
words. The EEPROM sends a "0" to acknowledge that it has received each word. This happens during
the ninth clock cycle.
STANDBY MODE:
The BL24C02A/BL24C04A/BL24C08A/BL24C16A features a low-power standby mode
which is enabled: (a) upon power-up and (b) after the receipt of the STOP bit and the completion of any
internal operations.
MEMORY RESET:
After an interruption in protocol, power loss or system reset, any two-wire part can be
reset by following these steps:
BL24C02A/04A/08A/16A Belling Proprietary Information. Unauthorized Photocopy and Duplication Prohibited
© 2016 Belling All Rights Reserved www.belling.com.cn
3-16
BL24C02A/04A/08A/16A
1. Clock up to 9 cycles.
2. Look for SDA high in each cycle while SCL is high.
3. Create a start condition.
Figure 2. Data Validity
SDA
SCL
DATA STABLE
DATA CHANGE
DATA STABLE
Figure 3. Start and Stop Definition
SDA
SCL
START
STOP
Figure 4. Output Acknowledge
SCL
1
8
9
DATA IN
DATA OUT
START
ACKNOWLEDGE
BL24C02A/04A/08A/16A Belling Proprietary Information. Unauthorized Photocopy and Duplication Prohibited
© 2016 Belling All Rights Reserved www.belling.com.cn
4-16
BL24C02A/04A/08A/16A
3.
Device Addressing
The 2K/4K/8K/16K EEPROM devices all require an 8-bit device address word following a start condition
to enable the chip for a read or write operation (see
Figure 5)
The device address word consists of a mandatory "1", "0" sequence for the first four most significant
bits as shown. This is common to all the Serial EEPROM devices.
The next 3 bits are fixed to zero for the 2K EEPROM.
For the 4K EEPROM, the next two bits are fixed to zero and the third bit being a memory page address
bit.
For the 8K EEPROM, the next one bit is fixed to zero and the next 2 bits being for memory page
addressing.
The 16K does not use any device address bits but instead the 3 bits are used for memory page
addressing. These page addressing bits on the 4K, 8K and 16K devices should be considered the most
significant bits of the data word address which follows.
The eighth bit of the device address is the read/write operation select bit. A read operation is initiated if
this bit is high and a write operation is initiated if this bit is low.
Upon a compare of the device address, the EEPROM will output a "0". If a compare is not made, the
chip will return to a standby state.
Figure 5. Device Address
MSB
2K
4K
8K
16K
4.
LSB
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
P2
0
0
P1
P1
0
P0
P0
P0
R/W
R/W
R/W
R/W
1
1
1
1
Write Operations
BYTE WRITE:
A write operation requires an 8-bit data word address following the device address word
and acknowledgment. Upon receipt of this address, the EEPROM will again respond with a "0" and then
clock in the first 8-bit data word. Following receipt of the 8-bit data word, the EEPROM will output a "0"
and the addressing device, such as a microcontroller, must terminate the write sequence with a stop
condition. At this time the EEPROM enters an internally timed write cycle, tWR, to the nonvolatile
BL24C02A/04A/08A/16A Belling Proprietary Information. Unauthorized Photocopy and Duplication Prohibited
© 2016 Belling All Rights Reserved www.belling.com.cn
6-16
FPGA/CPLD
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
