BL24C256A 256Kbits (32768×8)
Features
Compatible with all I
2
C bidirectional data
transfer protocol
Memory array:
–
–
–
–
–
Page Write within 3 ms
Partial Page Writes Allowed
Write Protect Pin for Hardware Data Protection
Schmitt Trigger, Filtered Inputs for Noise
Suppression
High-reliability
–
–
256 Kbits (32 Kbytes) of EEPROM
Page size: 64 bytes
Additional Write lockable page
1 MHz
Single supply voltage and high speed:
–
Endurance: 1 Million Write Cycles
Data Retention: 100 Years
HBM 8000V
Random and sequential Read modes
Write:
–
Enhanced ESD/Latch-up protection
–
Byte Write within 3 ms
8-lead PDIP/SOP/TSSOP/UDFN packages
Description
The BL24C256A provides 262144 bits of serial
electrically erasable and programmable read-
only memory (EEPROM), organized as 32768
words of 8 bits each.
The device is optimized for use in many
industrial and commercial applications where
low-power
essential.
and
low-voltage
operation
are
The BL24C256A offers an additional page,
named the Identification Page (64 bytes). The
Identification Page can be used to store
sensitive application parameters which can be
(later) permanently locked in Read-only mode.
Pin Configuration
８-lead
PDIP
８-lead
SOP
８-lead
TSSOP
８-pad
DFN
A0
A1
A2
GND
１
２
３
４
8
7
6
5
VCC
WP
SCL
SDA
A0
A1
A2
GND
１
２
３
４
8
7
6
5
VCC
WP
SCL
SDA
A0
A1
A2
GND
１
２
３
４
8
7
6
5
VCC
WP
SCL
SDA
VCC
WP
8
7
1
2
3
4
A0
A1
A2
GND
SCL
6
SDA
5
Bottem view
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BL24C256A 256Kbits (32768×8)
Pin Descriptions
Pin Name
A0-A2
SDA
SCL
WP
GND
Vcc
Type
I
I/O
I
I
P
P
Table 1
Functions
Address Inputs
Serial Data
Serial Clock Input
Write Protect
Ground
Power Supply
Block Diagram
Vcc
GND
WP
SCL
SDA
START STOP
LOGIC
EN
SERIAL CONTROL
LOGIC
LOAD
CCMP
DEVICE ADDRESS
COMPARATOR
DATA RECOVERY
HIGH VOLTAGE
PUMP/TIMING
LOAD
INC
X DECODER
A0
A1
A2
DATA WORD
ADRESS COUNTER
EEPROM
Y DECODER
SERIAL MUX
DIN
DOUT/ACKNOWLEDGE
DOUT
Figure 1
DEVICE/PAGE ADDRESSES (A2, A1 and A0):
The A2, A1 and A0 pins are device address inputs that are hard
wire for the BL24C256A. Eight 256K devices may be addressed on a single bus system (device
addressing is discussed in detail under the Device Addressing section).
SERIAL DATA (SDA):
The SDA pin is bi-directional for serial data transfer. This pin is open-drain driven
and may be wire-ORed with any number of other open-drain or open- collector devices.
SERIAL CLOCK (SCL):
The SCL input is used to positive edge clock data into each EEPROM device
and negative edge clock data out of each device.
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BL24C256A 256Kbits (32768×8)
WRITE PROTECT (WP):
The BL24C256A has a Write Protect pin that provides hardware data protection.
The Write Protect pin allows normal read/write operations when connected to ground (GND). When
the Write Protection pin is connected to Vcc, the write protection feature is enabled and operates as
shown in the following
Table 2.
WP Pin Status
At VCC
At GND
Table 2
BL24C256A
Full(256K)Array
Normal Read/Write Operations
Functional Description
1.
Memory Organization
BL24C256A, 256K SERIAL EEPROM:
Internally organized with 256 pages of 64 bytes each, the 256K
requires a 15-bit data word address for random word addressing.
2.
Device Operation
CLOCK and DATA TRANSITIONS:
The SDA pin is normally pulled high with an external device. Data on the
SDA pin may change only during SCL low time periods (see
Figure 2).
Data changes during SCL high
periods will indicate a start or stop condition as defined below.
START CONDITION:
A high-to-low transition of SDA with SCL high is a start condition which must
precede any other command (see
Figure 3).
STOP CONDITION:
A low-to-high transition of SDA with SCL high is a stop condition. After a read
sequence, the stop command will place the EEPROM in a standby power mode (see
Figure 3).
ACKNOWLEDGE:
All addresses and data words are serially transmitted to and from the EEPROM in 8-bit
words. The EEPROM sends a "0" to acknowledge that it has received each word. This happens during
the ninth clock cycle.
STANDBY MODE:
The BL24C256A features a low-power standby mode which is enabled: (a) upon power-
up and (b) after the receipt of the STOP bit and the completion of any internal operations.
MEMORY RESET:
After an interruption in protocol, power loss or system reset, any two-wire part can be
reset by following these steps:
1. Clock up to 9 cycles.
2. Look for SDA high in each cycle while SCL is high.
3. Create a start condition.
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BL24C256A 256Kbits (32768×8)
Figure 2. Data Validity
SDA
SCL
DATA STABLE
DATA CHANGE
DATA STABLE
Figure 3. Start and Stop Definition
SDA
SCL
START
STOP
Figure 4. Output Acknowledge
SCL
1
8
9
DATA IN
DATA OUT
START
ACKNOWLEDGE
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BL24C256A 256Kbits (32768×8)
3.
Device Addressing
The 256K EEPROM devices all require an 8-bit device address word following a start condition to enable
the chip for a read or write operation (see
Figure 5)
The device address word consists of a mandatory "1", "0" sequence for the first four most significant
bits as shown. This is common to all the Serial EEPROM devices.
The 256K EEPROM uses A2, A1 and A0 device address bits to allow as much as eight devices on the
same bus. These 3 bits must be compared to their corresponding hardwired input pins. The A2, A1 and
A0 pins use an internal proprietary circuit that biases them to a logic low condition if the pins are
allowed to float.
The eighth bit of the device address is the read/write operation select bit. A read operation is initiated if
this bit is high and a write operation is initiated if this bit is low.
Upon a compare of the device address, the EEPROM will output a "0". If a compare is not made, the
chip will return to a standby state.
DATA SECURITY:
The BL24C256A has a hardware data protection scheme that allows the user to write
protect the entire memory when the WP pin is at VCC.
4.
Write Operations
BYTE WRITE:
A write operation requires an 8-bit data word address following the device address word
and acknowledgment. Upon receipt of this address, the EEPROM will again respond with a "0" and then
clock in the first 8-bit data word. Following receipt of the 8-bit data word, the EEPROM will output a "0"
and the addressing device, such as a microcontroller, must terminate the write sequence with a stop
condition. At this time the EEPROM enters an internally timed write cycle, tWR, to the nonvolatile
memory. All inputs are disabled during this write cycle and the EEPROM will not respond until the write
is complete (see
Figure 6).
PAGE WRITE:
A write operation requires an 8-bit data word address following the device address word
and acknowledgment. Upon receipt of this address, the EEPROM will again respond with a "0" and then
clock in the first 8-bit data word. Following receipt of the 8-bit data word, the EEPROM will output a "0"
and the addressing device, such as a microcontroller, must terminate the write sequence with a stop
condition. At this time the EEPROM enters an internally timed write cycle, tWR, to the nonvolatile
memory. All inputs are disabled during this write cycle and the EEPROM will not respond until the write
is complete (see
Figure 7).
The data word address lower five bits are internally incremented following the receipt of each data
word. The higher data word address bits are not incremented, retaining the memory page row location.
When the word address, internally generated, reaches the page boundary, the following byte is placed
at the beginning of the same page. If more than 64 data words are transmitted to the EEPROM, the
data word address will
"roll over"
and previous data will be overwritten.
WRITE IDENTIFICATION PAGE:The
Identification Page (64 bytes) is an additional page which can be
written and (later) permanently locked in Read-only mode. It is written by issuing the Write
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