BL24C128A 128K bits (16,384×8)
Features
Compatible with all data transfer protocol
–
1 MHz
–
400 kHz
–
100 kHz
Memory array:
–
128 Kbit (16 Kbytes) of EEPROM
–
Page size: 64 bytes
–
Additional Write lockable page
Single supply voltage and high speed:
–
1 MHz
Write:
–
Byte Write within 3 ms
–
Page Write within 3 ms
Operating Ambient Temperature:
–
From -40
°
up to +85
°
C
C
High-reliability
–
Endurance: 1 Million Write Cycles
–
Data Retention: 100 Years
Internally Organized:
–
BL24C128A, 16,384 X 8 (128K bits)
Two-wire Serial Interface
Schmitt Trigger, Filtered Inputs for Noise
Suppression
Bidirectional Data Transfer Protocol
Write Protect Pin for Hardware Data
Protection
Partial Page Writes Allowed
Self-timed Write Cycle (5 ms max)
8-lead PDIP/SOP/TSSOP/UDFN/WLCSP4
packages
Description
The BL24C128A provides 131,072 bits of serial electrically erasable and programmable read-only
memory (EEPROM), organized as 16,384 words of 8 bits each. The device is optimized for use in
many industrial and commercial applications where low-power and low-voltage operation are
essential. The BL24C128A is available in space-saving 8-lead PDIP, 8-lead SOP, and 8-lead
TSSOP ，WLCSP4 packages and is accessed via a two-wire serial interface. In addition, the
BL24C128A is available in 1.7V (1.7V to 5.5V) version.
Pin Configuration
８-lead
PDIP
８-lead
SOP
８-lead
TSSOP
８-pad
DFN
WLCSP4
1
1
A0
2
A1
3
A2
4
GND
B
SCL
SDA
2
A0
A1
A2
GND
１
２
３
４
8
7
6
5
VCC
WP
SCL
SDA
A0
A1
A2
GND
１
２
３
４
8
7
6
5
VCC
WP
SCL
SDA
A0
A1
A2
GND
１
２
３
４
8
7
6
5
VCC
WP
SCL
SDA
VCC
WP
8
7
A
Vcc
Vss
SCL
6
SDA
5
Bottem view
Marking side
(top view)
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BL24C128A 128K bits (16,384×8)
Pin Descriptions
Pin Name
A0-A2
SDA
SCL
WP
GND
Vcc
Type
I
I/O&Open-drain
I
I
P
P
Table 1
Functions
Address Inputs
Serial Data
Serial Clock Input
Write Protect
Ground
Power Supply
Block Diagram
Vcc
GND
WP
SCL
SDA
START STOP
LOGIC
EN
SERIAL CONTROL
LOGIC
LOAD
CCMP
DEVICE ADDRESS
COMPARATOR
DATA RECOVERY
HIGH VOLTAGE
PUMP/TIMING
LOAD
INC
X DECODER
A0
A1
A2
DATA WORD
ADRESS COUNTER
EEPROM
Y DECODER
SERIAL MUX
DIN
DOUT/ACKNOWLEDGE
DOUT
DEVICE/PAGE ADDRESSES (A2, A1 and A0):
The A2, A1 and A0 pins are device address inputs that are
hard wire for the BL24C128A. Eight 128K devices may be addressed on a single bus system (device
addressing is discussed in detail under the Device Addressing section).
SERIAL DATA (SDA):
The SDA pin is bi-directional for serial data transfer. This pin is open-drain driven
and may be wire-ORed with any number of other open-drain or open- collector devices.
SERIAL CLOCK (SCL):
The SCL input is used to positive edge clock data into each EEPROM device and
negative edge clock data out of each device.
WRITE PROTECT (WP):
The BL24C128A has a Write Protect pin that provides hardware data protection.
The Write Protect pin allows normal read/write operations when connected to ground (GND). When
the Write Protection pin is connected to Vcc, the write protection feature is enabled and operates as
BL24C128A 128Kbits (16,384×8) Belling Proprietary Information. Unauthorized Photocopy and Duplication Prohibited
© 2016 Belling All Rights Reserved www.belling.com.cn
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BL24C128A 128K bits (16,384×8)
shown in the following Table 2.
WP Pin Status
At VCC
At GND
Table2
BL24C128A
Full(128K)Array
Normal Read/Write Operations
Functional Description
1. Memory Organization
BL24C128A, 128K SERIAL EEPROM:
Internally organized with 256 pages of 64 bytes each, the 128K
requires a 14-bit data word address for random word addressing.
2. Device Operation
CLOCK and DATA TRANSITIONS:
The SDA pin is normally pulled high with an external device. Data on
the SDA pin may change only during SCL low time periods (see Figure 1). Data changes during SCL
high periods will indicate a start or stop condition as defined below.
START CONDITION:
A high-to-low transition of SDA with SCL high is a start condition which must
precede any other command (see Figure 2).
STOP CONDITION:
A low-to-high transition of SDA with SCL high is a stop condition. After a read
sequence, the stop command will place the EEPROM in a standby power mode (see Figure 2).
ACKNOWLEDGE:
All addresses and data words are serially transmitted to and from the EEPROM in 8-bit
words. The EEPROM sends a "0" to acknowledge that it has received each word. This happens during
the ninth clock cycle.
STANDBY MODE:
The BL24C128A features a low-power standby mode which is enabled: (a) upon
power-up and (b) afer the receipt of the STOP bit and the completion of any internal operations.
MEMORY RESET:
After an interruption in protocol, power loss or system reset, any two-wire part can
be reset by following these steps:
1. Clock up to 9 cycles.
2. Look for SDA high in each cycle while SCL is high.
3. Create a start condition
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BL24C128A 128K bits (16,384×8)
Figure 1. Data Validity
SDA
SCL
DATA STABLE
DATA CHANGE
DATA STABLE
Figure 2. Start and Stop Definition
SDA
SCL
START
STOP
Figure 3. Output Acknowledge
SCL
1
8
9
DATA IN
DATA OUT
START
ACKNOWLEDGE
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BL24C128A 128K bits (16,384×8)
3. Device Addressing
The 128K EEPROM devices all require an 16-bit device address word following a start condition to
enable the chip for a read or write operation (see Figure 4)
The device address word consists of a mandatory "1", "0" sequence for the first four most
significant bits as shown. This is common to all the Serial EEPROM devices.
The 128K EEPROM uses A2, A1 and A0 device address bits to allow as much as eight devices on the
same bus. These 3 bits must be compared to their corresonding hardwired input pins. The A2, A1
and A0 pins use an internal proprietary circuit that biases them to a logic low condition if the pins
are allowed to float.
The eighth bit of the device address is the read/write operation select bit. A read operation is
initiated if this bit is high and a write operation is initiated if this bit is low.
Upon a compare of the device address, the EEPROM will output a "0". If a compare is not made, the
chip will return to a standby state.
DATA SECURITY:
The BL24C128A has a hardware data protection scheme that allows the user
write protect the entire memory when the WP pin is at VCC.
to
4. Write Operations
BYTE WRITE:
A write operation requires two 8-bit data word address following the device address
word and acknowledgment. Upon receipt of every 8-bit address, the EEPROM will respond with a
"0" and then clock in the first 8-bit data word. Following receipt of the 8-bit data word, the
EEPROM will output a "0" and the addressing device, such as a microcontroller, must terminate the
write sequence with a stop condition. At this time the EEPROM enters an internally timed write
cycle, tWR, to the nonvolatile memory. All inputs are disabled during this write cycle and the
EEPROM will not respond until the write is complete (see Figure 5).
PAGE WRITE:
The 128K EEPROM is capable of an 64-byte page writes. A page write is initiated the
same as a byte write, but the microcontroller does not send a stop condition after the first data
word is clocked in. Instead, after the EEPROM acknowledges receipt of the first data word, the
microcontroller can transmit up to 63 more data words. The EEPROM will respond with a
“0”
after
each data word received. The microcontroller must terminate the page write sequence with a stop
condition (see Figure 6).
The data word address lower six bits are internally incremented following the receipt of each data
word. The higher data word address bits are not incremented, retaining the memory page row
location. When the word address, internally generated, reaches the page boundary, the following
byte is placed at the beginning of the same page. If more than 64data words are transmitted to the
EEPROM, the data word address will
“roll
over” and previous data will be overwritten.
ACKNOWLEDGE POLLING:
Once the internally timed write cycle has started and the EEPROM inputs
are disabled, acknowledge polling can be initiated. This involves sending a start condition followed
by the device address word. The read/write bit is representative of the operation desired. Only if the
internal write cycle has completed will the EEPROM respond with a "0", allowing the read or write
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