AZ1043-04F
Ultra Low Capacitance ESD Protection Array
For High Speed I/O Port
Features
ESD Protect for Transition Minimized Differential
Signaling (TMDS) channels
Protects four I/O lines
Provide ESD protection for each line to
IEC 61000-4-2 (ESD) ±15kV (air), ±11kV (contact)
IEC 61000-4-5 (Lightning) 4A (8/20µs)
µ
Consumer Electronics
Set Top Box
DVDRW Players
Graphics Cards
Description
AZ1043-04F is a design which includes ESD
rated diode arrays to protect high speed data
interfaces. The AZ1043-04F has been
specifically designed to protect sensitive
components which are connected to data and
transmission lines from over-voltage caused by
Electrostatic Discharging (ESD).
AZ1043-04F is a unique design which includes
ESD rated, ultra low capacitance steering diodes
and a unique design of clamping cell which is an
equivalent TVS diode
in a single package. During
transient conditions, the steering diodes direct
the transient to either the internal ESD line or to
ground line. The internal unique design of
clamping cell prevents over-voltage on the
internal ESD line and on the I/O line, which is
protecting any downstream components.
AZ1043-04F may be used to meet the ESD
immunity requirements of IEC 61000-4-2, Level 4
(±15kV air,
±8kV
contact discharge).
For operating voltage of 3.3V and below
Ultra low capacitance : 0.45pF typical
Fast turn-on and Low clamping voltage
Array of ESD rated diodes with internal
equivalent TVS (Transient Voltage
Suppression) diode
Simplified layout for HDMI connectors
Solid-state silicon-avalanche and active circuit
triggering technology
Green part
Applications
High Definition Multi-Media Interface (HDMI)
1.3, 1.4 and 2.0 version
DisplayPort interface
SATA and eSATA interface
USB3.0
Digital Visual Interface (DVI)
USB2.0 up to 480Mb/s
IEEE 1394 up to 3.2 Gb/s
Ethernet port: 10/100/1000 Mb/s
Desktop and Notebooks PCs
Circuit Diagram
Pin Configuration
Line-1
Line-2
GND
1
2
3
4
5
10 NC
9
8
7
6
NC
GND
NC
NC
1
3,8
2
4
5
Line-3
Line-4
DFN2510P10E (Top View)
Revision 2014/11/20
©2014-2015 Amazing Micro.
1
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AZ1043-04F
Ultra Low Capacitance ESD Protection Array
For High Speed I/O Port
SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Peak Pulse Current (tp= 8/20µs)
Operating Voltage (I/O pin-GND)
ESD per IEC 61000-4-2 (Air)
ESD per IEC 61000-4-2 (Contact)
Lead Soldering Temperature
Operating Temperature
Storage Temperature
SYMBOL
I
PP
V
DC
V
ESD
T
SOL
T
OP
T
STO
ELECTRICAL CHARACTERISTICS
PARAMETER
Reverse Stand-Off
Voltage
Channel Leakage
Current
Reverse Breakdown
Voltage
Forward Voltage
ESD Clamping
Voltage
ESD Dynamic
Turn-on Resistance
Channel Input
Capacitance
Channel to Channel
Input Capacitance
SYMBOL
V
RWM
I
CH-Leak
V
BV
V
F
V
clamp
R
dynamic
C
IN
C
CROSS
CONDITIONS
Pin-1,-2,-4,-5 to pin-3,-8, T=25
o
C
V
Pin-1,-2,-4,-5
= 3.3V, V
Pin-3,-8
= 0V,
T=25
o
C
I
BV
= 1mA, T=25
o
C, pin-1,-2,-4,-5 to
pin-3,-8
I
F
= 15mA, T=25
o
C, pin-3,-8 to
pin-1,-2,-4,-5
IEC 61000-4-2 +6kV, T=25
o
C,
Contact mode, any I/O pin to Ground
IEC 61000-4-2, 0~+6kV, T=25
o
C,
Contact mode, any I/O pin to Ground
V
pin-3,-8
= 0V,
V
IN
= 1.65V,
f = 1MHz,
T=25
o
C, any I/O pin to Ground
V
pin-3,-8
= 0V,
V
IN
= 1.65V,
f = 1MHz,
T=25
o
C, between I/O pins
4.5
0.9
10.5
0.3
0.45
0.04
0.65
0.08
1.1
MIN
TYP
MAX
UNITS
RATING
4
(GND – 0.5) to 3.6
15
11
260 (10 sec.)
-55 to +85
-55 to +150
UNITS
A
V
kV
o
o
o
C
C
C
3.3
1
V
µ
A
V
V
V
Ω
pF
pF
Revision 2014/11/20
©2014-2015 Amazing Micro.
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AZ1043-04F
Ultra Low Capacitance ESD Protection Array
For High Speed I/O Port
Typical Characteristics
0.8
0.7
Input Capacitance (pF)
0.6
0.5
0.4
0.3
0.2
0.1
0.0
0.0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0 3.3
Input Voltage (V)
Typical Variation of CIN vs. VIN
f = 1MHz, T=25 oC,
0.10
0.09
Input Capacitance (pF)
0.08
0.07
0.06
0.05
0.04
0.03
0.02
0.01
Typical Variation of CIO-to-IO vs. VIN
o
f = 1MHz, T=25 C,
0.00
0.0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0 3.3
Input Voltage (V)
Insertion Loss S21 (IO-to-GND)
0
20
10
Analog Cross Talk
Analog Cross Talk (dB)
8.3GHz : -3dB
-3
Insertion Loss (dB)
-6
-9
-12
-15
-18
-21
-24
-27
-30
1e+8
1e+9
1e+10
0
-10
-20
-30
-40
-50
-60
-70
-80
1e+8
1e+9
Frequency (Hz)
Frequency (Hz)
Transmission Line Pulsing (TLP) Current (A)
Transmission Line Pulsing (TLP) Measurement
18
16
14
V_pulse
12
10
8
6
4
2
0
0
Pulse from a
transmission line
TLP_I
100ns
+
TLP_V
-
DUT
I/O to GND
1
2
3
4
5
6
7
8
9
10
11
12
Transmission Line Pulsing (TLP) Voltage (V)
Revision 2014/11/20
©2014-2015 Amazing Micro.
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AZ1043-04F
Ultra Low Capacitance ESD Protection Array
For High Speed I/O Port
Applications Information
The AZ1043-04F is designed to protect four
data lines from transient over-voltage (such as
ESD stress pulse). The device connection of
AZ1043-04F is shown in the Fig. 1. In Fig. 1, the
four protected data lines are connected to the
ESD protection pins (pin1, pin2, pin4, and pin5)
of AZ1043-04F. The ground pins (pin3 and pin8)
of AZ1043-04F are the negative reference pins.
These pins should be directly connected to the
GND rail of PCB (Printed Circuit Board). To get
minimum parasitic inductance, the path length
should keep as short as possible.
AZ1043-04F can provide ESD protection for
4 I/O signal lines simultaneously. If the number of
I/O signal lines is less than 4, the unused I/O pins
can be simply left as NC pins.
To
I/O-port
Connector
I/O 1
data
data
line
line
I/O 1
I/O 2
Line-1
Line-2
GND
Line-3
Line-4
1
10
NC
NC
GND
I/O 2
To
Protected
IC
3
4
5
AZ1043-04F
2
9
8
7
6
NC
NC
I/O 3
To
Protected
IC
To
I/O-port
Connector
I/O 3
data
I/O 4
data
line
line
I/O 4
Fig. 1 Data lines connection of AZ1043-04F.
B. Application
AZ1043-04F is designed for protecting high
speed I/O ports from over-voltage caused by
Electrostatic Discharging (ESD). Thus, a lot of
kinds of high speed I/O ports can be the
applications of AZ1043-04F, especially, the HDMI
port.
HDMI Protection for High and Low speed
signals
The HDMI Compliance Test Specification
(CTS) requires sink (receiver) ports maintain a
differential impedance of 100 Ohms +/- 15%.
ESD protection devices have an inherent
Revision 2014/11/20
©2014-2015 Amazing Micro.
junction capacitance. Even a small amount of
added capacitance on a HDMI port will cause the
impedance of the differential pair to drop. Thus,
some form of compensation to the layout will be
required to bring the differential pairs back within
the required 100 Ohm +/- 15% range. The higher
the added capacitance, the more extreme the
modifications will need to be. If the added
capacitance is too high, compensation may not
even be possible. The AZ1043-04F presents
0.45pF
capacitance to each differential signal
while being rated to handle >8kV ESD contact
discharges (>15kV air discharge) as outlined in
IEC 61000-4-2. Therefore, it is possible to
make
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AZ1043-04F
Ultra Low Capacitance ESD Protection Array
For High Speed I/O Port
none
adjustment to the board layout parameters
to compensate for the added capacitance of the
AZ1043-04F. Figure 2 shows how to implement
the AZ1043-04F in a HDMI application.
The AZ1043-04F is designed for allowing the
traces to run straight through the device to
simplify the PCB layout. As shown in Figure 2,
the best way to design the PCB trace is using the
flow through layout. The solid line represents the
PCB trace. Note that the PCB traces are used to
connect the pin pairs for each line (pin 1 to pin 10,
pin 2 to pin 9, pin 4 to pin 7, pin 5 to pin 6). For
TMDS_D2+
TMDS_GND
TMDS_D2-
TMDS_D1+
TMDS_GND
TMDS_D1-
TMDS_D0+
TMDS_GND
TMDS_D0-
TMDS_CK+
TMDS_GND
TMDS_CK-
CE_REMOTE
N/C
DDC_CLK
DDC_DAT
GND
+5V OUT
HOTPLUG_DET
example, line 1 enters at pin 1 and exits at Pin 10
and the PCB trace connects pin 1 and 10
together. Lines 2, 3, and 4 have the same way of
connection. The ground pins (pin3 and pin8) of
AZ1043-04F are the negative reference pins.
These pins should be directly connected to the
GND plane of PCB. To get minimum parasitic
inductance, the path length should keep as short
as possible.
In Figure 2, the none-TMDS
signals, DDC_CLK, DDC_DAT, CE_REMOTE,
and HOTPLUG_DET, can be protected with
another low cost part, e.g., AZC199-04S.
Line-1
Line-2
GND
Line-3
Line-4
1
2
3
4
5
10
TMDS_D2+
NC
NC
GND
NC
NC
TMDS_D2-
AZ1043-04F
9
8
7
6
TMDS_D1+
TMDS_D1-
TMDS_D0+
Line-1
Line-2
GND
Line-3
Line-4
1
10
NC
NC
GND
NC
NC
TMDS_D0-
AZ1043-04F
2
3
4
5
9
8
7
6
TMDS_CK+
TMDS_CK-
CE_REMOTE
Via hole to GND
3
GND
2
DDC_CLK
1
4
HDMI
Connector
Fig. 2 HDMI Protection for High and Low speed signals.
Revision 2014/11/20
©2014-2015 Amazing Micro.
5
AZC199-04S
5
+5V
6
Via hole to +5V
DDC_DAT
C=100nF
(optional)
Via hole to GND
HOTPLUG_DET
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PCB设计
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