AZC015-04F
Low Capacitance ESD Protection Array
For High Speed Data Interfaces
Features
ESD Protect for 4 high-speed I/O channels
Provide ESD protection for each channel to
IEC 61000-4-2 (ESD) ±18kV (air), ±14kV (contact)
IEC 61000-4-4 (EFT) (5/50ns) Level-3, 20A for I/O,
80A for Power
IEC 61000-4-5 (Lightning) 6.5A (8/20µs)
line, protecting any downstream components.
AZC015-04F may be used to meet the ESD
immunity requirements of IEC 61000-4-2, Level 4
(± 15kV air,
±8kV
contact discharge).
Circuit Diagram
5
5V operating voltage
Low capacitance : 1.3pF typical
Fast turn-on and Low clamping voltage
Array of surge rated diodes with internal
equivalent TVS diode
Small package saves board space
Solid-state silicon-avalanche and active circuit
triggering technology
Green part available
1
3
4
6
2
Applications
I/O ports and Buses of Mobile Devices
USB2.0 Power and Data lines protection
Notebook and PC Computers
Monitors and Flat Panel Displays
IEEE 1394 Firewire Ports
Video Graphics Cards
SIM ports
Pin Configuration
I/O 4
VDD
I/O 3
Description
AZC015-04F is a high performance and low cost
design which includes surge rated diode arrays
to protect high speed data interfaces. The
AZC015-04F family has been specifically
designed to protect sensitive components, which
are connected to data and transmission lines,
from over-voltage caused by Electrostatic
Discharging (ESD), Electrical Fast Transients
(EFT), and Lightning.
AZC015-04F is a unique design which includes
surge rated, low capacitance steering diodes and
a unique design of clamping cell which is an
equivalent TVS diode
in a single package. During
transient conditions, the steering diodes direct
the transient to either the power supply line or to
the ground line. The internal unique design of
clamping cell prevents over-voltage on the power
Revision 2011/07/30
©2011-2012 Amazing Micro.
1
6
5
4
1
I/O 1
2
GND
3
I/O 2
QFN1616P6E (Top View)
www.amazingIC.com
AZC015-04F
Low Capacitance ESD Protection Array
For High Speed Data Interfaces
SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
PARAMETER
PARAMETER
I
PP
Peak Pulse Current (tp =8/20µs) @ 25
o
C
Operating Supply Voltage (VDD-GND)
V
DC
o
ESD per IEC 61000-4-2 (Air)(I/O to GND) @ 25 C
V
ESD_I/O
ESD per IEC 61000-4-2 (Contact) (I/O to GND) @ 25
o
C
ESD per IEC 61000-4-2 (Air)(I/O to GND) @ 85
o
C
V
ESD_I/O
ESD per IEC 61000-4-2 (Contact) (I/O to GND) @ 85
o
C
ESD per IEC 61000-4-2(Air)(VDD-GND) @ 85
o
C
V
ESD_VDD
ESD per IEC 61000-4-2(Contact) (VDD-GND) @ 85
o
C
Lead Soldering Temperature
T
SOL
Operating Temperature
T
OP
Storage Temperature
T
STO
DC Voltage at any I/O pin
V
IO
RATING
6.5
6
21
14
19
12
30
24
260 (10 sec.)
-55 to +85
-55 to +150
(GND – 0.5) to
(VDD + 0.5)
MIN
TYP
MAX
5
5
1
6
0.8
8.1
12.5
9
0.35
0.2
1.3
0.12
0.05
1.6
0.14
0.07
9
1
9
UNITS
A
V
kV
kV
kV
o
o
C
C
o
C
V
PARAMETER
Reverse Stand-Off
Voltage
Reverse Leakage
Current
Channel Leakage
Current
Reverse
Breakdown
Voltage
Forward Voltage
Clamping Voltage
ESD Clamping
Voltage –I/O
ESD Clamping
Voltage –VDD
ESD Dynamic
Turn-on
Resistance –I/O
ESD Dynamic
Turn-on
Resistance –VDD
Channel Input
Capacitance
Channel to
Channel Input
Capacitance
Variation of
Channel Input
Capacitance
Revision 2011/07/30
ELECTRICAL CHARACTERISTICS
SYMBOL
CONDITIONS
V
RWM
Pin 5 to pin 2, T=25
o
C
I
Leak
I
CH_Leak
V
BV
V
F
V
CL
V
clamp_io
V
clamp_VDD
R
dynamic_io
R
dynamic_VDD
C
IN
C
CROSS
△
C
IN
UNITS
V
µ
A
µ
A
V
V
V
V
V
Ω
Ω
pF
pF
pF
V
RWM
= 5V, T=25
o
C, Pin 5 to pin 2
V
Pin 5
= 5V, V
Pin 2
= 0V, T=25
o
C,
V
CH
= 0 ~ 5V
I
BV
= 1mA, T=25
o
C
Pin 5 to Pin 2
I
F
= 15mA, T=25
o
C
Pin 2 to Pin 5
I
PP
=5A, tp=8/20µs, T=25
o
C
Any Channel pin to Ground
IEC 61000-4-2 +6kV, T=25
o
C,
Contact mode, Any Channel pin to
Ground
IEC 61000-4-2 +6kV, T=25
o
C,
Contact mode, VDD pin to Ground
IEC 61000-4-2 0~+6kV, T=25
o
C,
Contact mode, Any Channel pin to
Ground
IEC 61000-4-2 0~+6kV, T=25
o
C,
Contact mode, VDD pin to Ground
V
pin5
= 5V, V
pin2
= 0V,
V
IN
= 2.5V,
f =
1MHz, T=25
o
C, Any Channel pin
to Ground
V
pin5
= 5V, V
pin2
= 0V,
V
IN
= 2.5V,
f =
1MHz, T=25
o
C , Between
Channel pins
V
pin5
= 5V, V
pin2
= 0V,
V
IN
= 2.5V,
f =
1MHz, T=25
o
C , Channel_x pin to
Ground - Channel_y pin to Ground
2
©2011-2012 Amazing Micro.
www.amazingIC.com
AZC015-04F
Low Capacitance ESD Protection Array
For High Speed Data Interfaces
Typical Characteristics
Power Derating Curve
110
100
% of Rated Power or I
PP
90
Clamping Voltage (V)
12
11
10
9
8
7
6
5
4
3
2
1
Waveform
Parameters:
tr=8µs
µ
td=20µs
µ
Clamping Voltage vs. Peak Pulse Current
80
70
60
50
40
30
20
10
0
0
25
50
75
100
o
I/O pin to GND pin
125
150
0
4.5
5.0
5.5
6.0
6.5
7.0
7.5
Ambient Temperature, T
A
( C)
Peak pulse Current (A)
Forward Voltage vs. Forward Current
4.0
3.5
Forward Voltage (V)
3.0
2.5
2.0
1.5
1.0
0.5
0.0
4.5
I/O pin to GND pin
Waveform
Parameters:
tr=8µs
µ
td=20µs
µ
Typical Variation of CIN vs. VIN
2.0
1.8
Input Capacitance (pF)
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
o
VDD = 5V, GND = 0V, f = 1MHz, T=25 C,
5.0
5.5
6.0
6.5
7.0
7.5
0
1
2
3
4
5
Peak pulse Current (A)
Typical Variation of CIN vs. Temp
1.50
1.45
Input Capacitance (pF)
1.40
1.35
1.30
1.25
1.20
1.15
1.10
1.05
1.00
20
VDD = 5V, GND = 0V, VIN = 2.5V, f = 1MHz,
Input Voltage (V)
Transmission Line Pulsing (TLP) Current (A)
Transmission Line Pulsing (TLP) Measurement
18
16
14
V_pulse
12
10
8
6
4
2
0
0
Pulse from a
transmission line
TLP_I
100ns
+
TLP_V
-
DUT
I/O to GND
40
60
80
100
120
2
4
6
8
10
12
14
Temperature (oC)
Transmission Line Pulsing (TLP) Current (A)
Transmission Line Pulsing (TLP) Measurement
18
16
14
V_pulse
Transmission Line Pulsing (TLP) Voltage (V)
12
10
8
6
4
2
0
0
Pulse from a
transmission line
TLP_I
100ns
+
TLP_V
-
DUT
VDD to GND
1
2
3
4
5
6
7
8
9
10
Transmission Line Pulsing (TLP) Voltage (V)
Revision 2011/07/30
©2011-2012 Amazing Micro.
3
www.amazingIC.com
AZC015-04F
Low Capacitance ESD Protection Array
For High Speed Data Interfaces
Applications Information
A. Design Considerations
The ESD protection scheme for system I/O
connector is shown in the Fig. 1. In Fig. 1, the
diodes D1 and D2 are general used to protect
data line from ESD stress pulse. If the power-rail
ESD clamping circuit is not placed between VDD
and GND rails, the positive pulse ESD current
(I
ESD1
) will pass through the ESD current path1.
Thus, the ESD clamping voltage V
CL
of data line
can be described as follow:
V
CL
= Fwd voltage drop of D1 + supply voltage of
VDD rail + L
1
×
d(I
ESD1
)/dt + L
2
×
d(I
ESD1
)/dt
Where L
1
is the parasitic inductance of data line,
and L
2
is the parasitic inductance of VDD rail.
An ESD current pulse can rise from zero to its
peak value in a very short time. As an example, a
level 4 contact discharge per the IEC61000-4-2
standard results in a current pulse that rises from
zero to 30A in 1ns. Here d(I
ESD1
)/dt can be
approximated by
∆I
ESD1
/∆t, or 30/(1x10-9). So
just 10nH of total parasitic inductance (L
1
and L
2
combined) will lead to over 300V increment in
V
CL
! Besides, the ESD pulse current which is
directed into the VDD rail may potentially
damage any components that are attached to
that rail. Moreover, it is common for the forward
voltage drop of discrete diodes to exceed the
damage threshold of the protected IC. This is due
to the relatively small junction area of typical
discrete components. Of course, the discrete
diode is also possible to be destroyed due to its
power dissipation capability is exceeded.
The AZC015-04F has an integrated
power-rail ESD clamped circuit between VDD
and GND rails. It can successfully overcome
previous disadvantages. During an ESD event,
the positive ESD pulse current (I
ESD2
) will be
directed through the integrated power-rail ESD
clamped circuit to GND rail (ESD current path2).
The clamping voltage V
CL
on the data line is
small and protected IC will not be damaged
because power-rail ESD clamped circuit offer a
low impedance path to discharge ESD pulse
current.
power-rail ESD
clamp ing circuit
AZC015-04F
L
2
I
ESD2
D1
I
ESD1
VDD rail
+
Vp
L
1
data line
_
VESD
+
Protected
IC
D2
V
CL
_
GND rail
ESD current path 1 (I
ESD1
)
ESD current path 2 (I
ESD2
)
Fig. 1
Revision 2011/07/30
Application of positive ESD pulse between data line and GND rail.
©2011-2012 Amazing Micro.
4
www.amazingIC.com
AZC015-04F
Low Capacitance ESD Protection Array
For High Speed Data Interfaces
B. Device Connection
The AZC015-04F is designed to protect four
data lines and power rails from transient
over-voltage (such as ESD stress pulse). The
device connection of AZC015-04F is shown in
the Fig. 2. In Fig. 2, the four protected data lines
are connected to the ESD protection pins (pin1,
pin3, pin4, and pin6) of AZC015-04F. The ground
pin (pin2) of AZC015-04F is a negative reference
pin. This pin should be directly connected to the
GND rail of PCB (Printed Circuit Board). To get
minimum parasitic inductance, the path length
should keep as short as possible. In addition, the
power pin (pin 5) of AZC015-04F is a positive
reference pin. This pin should directly connect to
the VDD rail of PCB. When pin 5 of AZC015-04F
is connected to the VDD rail, the leakage current
of ESD protection pin of AZC015-04F becomes
very small. Because the pin 5 of AZC015-04F is
directly connected to VDD rail, the VDD rail also
can be protected by the power-rail ESD clamped
circuit (not shown) of AZC015-04F.
AZC015-04F can provide protection for 4 I/O
signal lines simultaneously. If the number of I/O
signal lines is less than 4, the unused I/O pins
can be simply left as NC pins.
In some cases, systems are not allowed
to be reset or restart after the ESD stress
directly applying at the I/O-port connector.
Under this situation, in order to enhance the
sustainable ESD Level, a 0.1µF chip capacitor
µ
can be added between the VDD and GND rails.
The place of this chip capacitor should be as
close as possible to the AZC015-04F.
I/O 1
data line
data line
I/O 1
To
I/O-port
Connector
I/O 2
I/O 2
To
Protected
IC
1
6
AZC015-04F
VDD rail
*Optional
0.1µ F
µ
Chip Cap.
GND rail
2
5
3
4
To
I/O-port
Connector
I/O 3
I/O 3
data line
I/O 4
To
Protected
IC
data line
I/O 4
Fig. 2 Data lines and power rails connection of AZC015-04F.
Revision 2011/07/30
©2011-2012 Amazing Micro.
5
www.amazingIC.com
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