AZ1065-06F
Ultra Low Capacitance ESD Protection Array
For High Speed I/O Port
Features
ESD Protect for
Super Speed Differential
Signaling (above 5Gb/s)
channels
Protects six I/O lines and one V
DD
line
Provide ESD protection for each channel to
IEC 61000-4-2, (ESD)
±15kV (air), ±8kV (contact)
For 5V and below 5V operating voltage
Ultra low capacitance: 0.35pF max.
Fast turn-on and Low clamping voltage
Array of surge rated diodes with internal
equivalent TVS diode
Solid-state silicon-avalanche and active circuit
triggering technology
Back-drive protection for power-down mode
Green part
Description
AZ1065-06F is a design which includes ESD
rated diode arrays to protect high speed data
interfaces. The AZ1065-06F has been
specifically designed to protect sensitive
components which are connected to data and
transmission lines from over-voltage caused by
Electrostatic Discharging (ESD).
AZ1065-06F is a unique design which includes
surge rated, ultra low capacitance steering
diodes and a unique design of clamping cell
which is an
equivalent TVS diode
in a single
package. During transient conditions, the
steering diodes direct the transient to either the
power supply line or to ground line. The internal
unique design of clamping cell prevents
over-voltage on the power line, protecting any
downstream components. Besides, there is a
back-drive protection design in AZ1065-06F for
power-down mode operation.
AZ1065-06F may be used to meet the ESD
immunity requirements of IEC 61000-4-2, Level 4
(±15kV air,
±8kV
contact discharge).
Applications
USB3.0
HDMI 1.4
High Speed I/O Ports in Any Electronic
Product
Circuit Diagram
I/O-1
Pin Configuration
1
10
2
I/O-6
VDD
2
9
island
GND
NC
1
4
5
6
7
10
3
8
NC
9
I/O-2
4
7
I/O-5
I/O-3
5
6
I/O-4
DFN4120P10E
(Top View)
Revision 2011/05/15
©2011 Amazing Micro.
1
www.amazingIC.com
AZ1065-06F
Ultra Low Capacitance ESD Protection Array
For High Speed I/O Port
SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Operating Supply Voltage (VDD-GND)
ESD per IEC 61000-4-2 (Air)
ESD per IEC 61000-4-2 (Contact)
Lead Soldering Temperature
Operating Temperature
Storage Temperature
DC Voltage at any I/O pin
PARAMETER
V
DC
V
ESD
T
SOL
T
OP
T
STO
V
IO
RATING
6
±15
±8
260 (10 sec.)
-40 to +85
-55 to +150
(GND – 0.5) to (VDD + 0.5)
UNITS
V
kV
o
o
o
C
C
C
V
PARAMETER
Reverse Stand-Off
V
RWM
Voltage
Reverse Leakage
I
Leak
Current
Channel Leakage
I
CH-Leak
Current
Reverse Breakdown
V
BV
Voltage
Forward Voltage
V
F
ESD Clamping
V
clamp_io
Voltage –I/O
ESD Clamping
V
clamp_VDD
Voltage –VDD
ESD Dynamic
Turn-on
R
dynamic_io
Resistance –I/O
ESD Dynamic
R
dynamic_VDD
Turn-on
Resistance –VDD
Channel Input
Capacitance
Channel to Channel
Input Capacitance
C
IN
ELECTRICAL CHARACTERISTICS
SYMBOL
CONDITIONS
Pin 2 to pin 9, T=25
o
C.
V
RWM
= 5V, T=25
o
C, Pin 2 to pin 9.
V
Pin 2
= 5V, V
Pin 9
= 0V, T=25
o
C.
I
BV
= 1mA, T=25
o
C, Pin 2 to Pin 9.
I
F
= 15mA, T=25
o
C, Pin 9 to Pin 2.
IEC 61000-4-2 +6kV,T=25
o
C,Contact
mode, Any Channel pin to Ground.
IEC 61000-4-2 +6kV, T=25
o
C,
Contact mode, VDD pin to Ground.
IEC 61000-4-2, 0~+6kV,T=25
o
C,
Contact mode, Any Channel pin to
Ground.
IEC 61000-4-2, 0~+6kV, T=25
o
C,
Contact mode, VDD pin to Ground.
V
pin2
= 5V,V
pin9
= 0V,V
IN
= 2.5V,f
=
1MHz, T=25
o
C, Any Channel pin to
Ground.
V
pin2
= 5V,
V
pin9
= 0V,
V
IN
= 2.5V,
f =
1MHz, T=25
o
C , Between Channel
pins.
MIN
TYP
MAX
UNITS
5
2.5
1
6
0.8
13
10
0.35
1.2
V
µ
A
µ
A
V
V
V
V
Ω
0.2
Ω
0.27
0.35
pF
C
CROSS
0.05
0.07
pF
Revision 2011/05/15
©2011 Amazing Micro.
2
www.amazingIC.com
AZ1065-06F
Ultra Low Capacitance ESD Protection Array
For High Speed I/O Port
Typical Characteristics
0.50
0.45
Input Capacitance (pF)
Input Capacitance (pF)
0.40
0.35
0.30
0.25
0.20
0.0
VDD=5V
VDD=Floated
Typical Variation of CIN vs. VIN
f = 1MHz, T=25 oC,
0.10
0.09
0.08
0.07
0.06
0.05
0.04
0.03
0.02
0.01
Typical Variation of CIO-to-IO vs. VIN
VDD=Floated
VDD=5V
f = 1MHz, T=25 oC,
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
0.00
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
Input Voltage (V)
Input Voltage (V)
insertion Loss S21 (I/O-to-GND)
0
-3
Insertion Loss (dB)
-6
-9
-12
-15
-18
-21
-24
-27
-30
1e+8
1e+9
Frequency (Hz)
-60
1e+8
4.1GHz: -3dB
Analog Cross Talk
0
-10
-20
-30
-40
-50
VDD=5V
VDD=Floated
VDD=5V
VDD=Floated
Analog Cross Talk (dB)
1e+9
Frequency (Hz)
Transmission Line Pulsing (TLP) Current (A)
Transmission Line Pulsing (TLP) Measurement
18
16
14
V_pulse
VDD to GND
12
10
8
6
4
2
0
0
Pulse from a
transmission line
TLP_I
100ns
+
TLP_V
-
DUT
I/O to GND
1
2
3
4
5
6
7
8
9 10 11 12 13 14
Transmission Line Pulsing (TLP) Voltage (V)
Revision 2011/05/15
©2011 Amazing Micro.
3
www.amazingIC.com
AZ1065-06F
Ultra Low Capacitance ESD Protection Array
For High Speed I/O Port
Applications Information
A. Design Considerations
The ESD protection scheme for system I/O
connector is shown in the Fig. 1. In Fig. 1, the
diodes D1 and D2 are general used to protect
data line from ESD stress pulse. The diode D3 is
a back-drive protection design, which blocks the
DC back-drive current when the potential of I/O
pin is greater than that of VDD pin. If the
power-rail ESD clamping circuit is not placed
between VDD and GND rails, the positive pulse
ESD current (I
ESD1
) will pass through the ESD
current path1. Thus, the ESD clamping voltage
V
CL
of data line can be described as follow:
V
CL
= Fwd voltage drop of D1 + Breakdown
voltage drop of D3 + supply voltage of VDD
rail + L
1
×
d(I
ESD1
)/dt + L
2
×
d(I
ESD1
)/dt
Where L
1
is the parasitic inductance of data line,
and L
2
is the parasitic inductance of VDD rail.
An ESD current pulse can rise from zero to its
peak value in a very short time. As an example, a
level 4 contact discharge per the IEC61000-4-2
standard results in a current pulse that rises from
power-rail ESD
clamping circuit
AZ1065-06F
zero to 30A in 1ns. Here d(I
ESD1
)/dt can be
approximated by
∆I
ESD1
/∆t, or 30/(1x10
-9
). So just
10nH of total parasitic inductance (L
1
and L
2
combined) will lead to over 300V increment in
V
CL
! Besides, the ESD pulse current which is
directed into the VDD rail may potentially
damage any components that are attached to
that rail. Moreover, it is common for the forward
voltage drop of discrete diodes to exceed the
damage threshold of the protected IC. This is due
to the relatively small junction area of typical
discrete components. Of course, the discrete
diode is also possible to be destroyed due to its
power dissipation capability is exceeded.
The AZ1065-06F has an integrated
power-rail ESD clamped circuit between VDD
and GND rails. It can successfully overcome
previous disadvantages. During an ESD event,
the positive ESD pulse current (I
ESD2
) will be
directed through the integrated power-rail ESD
clamped circuit to GND rail (ESD current path2).
The clamping voltage V
CL
on the data line is
small and protected IC will not be damaged
because power-rail ESD clamped circuit offer a
low impedance path to discharge ESD pulse
current.
D3
I
ESD2
D1
I
ESD1
L
2
VDD rail
+
Vp
L
1
data line
_
VESD
+
Protected
IC
D2
V
CL
_
GND rail
ESD current path 1 (I
ESD1
)
ESD current path 2 (I
ESD2
)
Fig. 1
Revision 2011/05/15
Application of positive ESD pulse between data line and GND rail.
©2011 Amazing Micro.
4
www.amazingIC.com
AZ1065-06F
Ultra Low Capacitance ESD Protection Array
For High Speed I/O Port
B. Device Connection
The AZ1065-06F is designed to protect six
data lines and one power rail from transient
over-voltage (such as ESD stress pulse). The
device connection of AZ1065-06F is shown in the
Fig. 2. In Fig. 2, the six protected data lines are
connected to the ESD protection pins (pin1, pin4,
pin5, pin6, pin7, and pin10) of AZ1065-06F. The
ground pin (pin9) of AZ1065-06F is a negative
reference pin. This pin should be directly
connected to the GND rail of PCB (Printed Circuit
Board). To get minimum parasitic inductance, the
path length should keep as short as possible. In
addition, the power pin (pin 2) of AZ1065-06F is a
positive reference pin. This pin should directly
connect to the VDD rail of PCB., then the VDD
rail also can be protected by the power-rail ESD
clamped circuit (not shown) of AZ1065-06F.
To
I/O-port
Connector
VDD rail
*Optional
0.1µF
µ
Chip Cap.
1
AZ1065-06F can provide protection for 6 I/O
signal lines simultaneously. If the number of I/O
signal lines is less than 6, the unused I/O pins
can be simply left as NC pins.
In some cases, systems are not allowed to
be reset or restart after the ESD stress directly
applying at the I/O-port connector. Under this
situation, in order to enhance the sustainable
ESD Level, a 0.1µF chip capacitor can be added
between the VDD and GND rails. The place of
this chip capacitor should be as close as possible
to the AZ1065-06F.
In some cases, there isn’t power rail
presented on the PCB. Under this situation, the
power pin (pin 2) of AZ1065-06F can be left as
floating. The protection will not be affected, only
the load capacitance of I/O pins will be slightly
increased. Fig. 3 shows the detail connection.
data
10
data
line
line
To
Protected
IC
2
VDD
island
3
NC
4
9
GND
8
NC
7
data
data
data
line
line
line
line
To
Protected
IC
To
I/O-port
Connector
5
6
data
Fig. 2 Data lines and power rails connection of AZ1065-06F.
To
I/O-port
Connector
VDD
floated
1
data
10
data
line
line
To
Protected
IC
2
VDD
island
3
NC
4
9
GND
8
NC
7
data
data
data
line
line
line
line
To
Protected
IC
To
I/O-port
Connector
5
6
data
Fig. 3 Data lines and power rails connection of AZ1065-06F. VDD pin is left as floating when no
power rail presented on the PCB.
Revision 2011/05/15
©2011 Amazing Micro.
5
www.amazingIC.com
聊聊、笑笑、闹闹
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
