AZ6225-01F
Low Voltage Transient Voltage Suppressing Device
0402 DFN Package for ESD/Surge Protection
Features
ESD Protection for 1 line with Bi-directional
Provide ESD protection for the protected line to
IEC 61000-4-2 (ESD) ±30kV (air), ±30kV (contact)
IEC 61000-4-4 (EFT) 80A (5/50ns)
IEC 61000-4-5 (Lightning) 20A (8/20µs)
AZ6225-01F is a unique design which includes
proprietary clamping cell in a single package.
During transient conditions, the proprietary
clamping cell prevents over-voltage on the power
line or control/data lines, protecting any
downstream components.
AZ6225-01F may be used to meet the ESD
immunity requirements of IEC 61000-4-2, Level 4
(±15kV air,
±8kV
contact discharge).
For low operating voltage applications: 2.5V
0402 small DFN package
saves board space
Protect one I/O line or power line
Fast turn-on and Low clamping voltage
Solid-state silicon-avalanche and active circuit
triggering technology
Green Part
Circuit Diagram /
Pin Configuration
Applications
Mobile Phones
Hand Held Portable Applications
Computer Interfaces Protection
Microprocessors Protection
Serial and Parallel Ports Protection
Control Signal Lines Protection
Power lines on PCB Protection
Latchup Protection
1
2
DFN1006P2E (Bottom View)
Description
AZ6225-01F is a design which includes one
bi-directional surge rated clamping cell to protect
one power line, or one control line, or one low
speed data line in an electronic systems. The
AZ6225-01F has been specifically designed to
protect sensitive components which are
connected to power and control lines from
over-voltage damage and latch-up caused by
Electrostatic Discharging (ESD), Electrical Fast
Transients (EFT), Lightning, and Cable
Discharge Event (CDE).
Revision 2014/12/03
© 2014-2015 Amazing Micro.
1
www.amazingIC.com
AZ6225-01F
Low Voltage Transient Voltage Suppressing Device
0402 DFN Package for ESD/Surge Protection
SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Peak Pulse Current (tp=8/20µs)
Operating Supply Voltage (pin-1 to pin-2)
ESD per IEC 61000-4-2 (Air)
ESD per IEC 61000-4-2 (Contact)
Lead Soldering Temperature
Operating Temperature
Storage Temperature
T
SOL
T
OP
T
STO
SYMBOL
I
PP
V
DC
V
ESD
RATING
20
2.8
±30
±30
260 (10 sec.)
-55 to +85
-55 to +150
o
o
o
UNITS
A
V
kV
C
C
C
ELECTRICAL CHARACTERISTICS
PARAMETER
Reverse Stand-Off
Voltage
Reverse Leakage
Current
Reverse
Breakdown Voltage
SYMBOL
V
RWM
I
Leak
V
BV
T=25
o
C.
V
RWM
=
±2.5V,
T=25
o
C.
I
BV
= 1mA, T=25
o
C.
I
PP
=5A, tp=8/20µs, T=25
o
C.
Surge Clamping
Voltage
V
surge_CL
I
PP
=10A, tp=8/20µs, T=25
o
C.
I
PP
=20A, tp=8/20µs, T=25
o
C.
ESD Clamping
Voltage
ESD Dynamic
Turn-on Resistance
Channel Input
Capacitance
V
clamp
IEC 61000-4-2 +6kV, Contact mode,
T=25
o
C, I/O pin to GND
IEC 61000-4-2 0~+6kV, Contact
mode, T=25
o
C.
V
R
= 0V, f = 1MHz, T=25
o
C.
3.5
4.0
5.0
6.8
V
CONDITIONS
MINI
-2.5
TYP
MAX
2.5
2
UNITS
V
µA
V
5.0
V
R
dynamic
0.07
Ω
C
IN
62.5
80
pF
Revision 2014/12/03
© 2014-2015 Amazing Micro.
2
www.amazingIC.com
AZ6225-01F
Low Voltage Transient Voltage Suppressing Device
0402 DFN Package for ESD/Surge Protection
Typical Characteristics
Typical Variation of C
IN
vs. V
IN
75
70
Transmission Line Pulsing (TLP) Measurement
Pin1 to Pin2
18
V_pulse
16
Pulse from a
14
TLP_I
12
transmission line
+
100ns
10
TLP_V DUT
8
6
_
4
2
0
-2
-4
-6
-8
-10
-12
-14
-16
-18
-7 -6 -5 -4 -3 -2 -1
0
f = 1MHz, T = 25°C
65
60
55
50
45
40
35
30
-2.5
-2.0
-1.5
-1.0
-0.5
0.0
0.5
1.0
1.5
2.0
2.5
Transmission Line Pulsing (TLP) Current (A)
80
Input Capacitance (pF)
Pin1 to Pin2
1
2
3
4
5
6
7
Input Voltage (V)
Transmission Line Pulsing (TLP) Voltage (V)
Clamping Voltage vs. Peak Pulse Current
10
9
8
Pin1 to Pin2
Pin2 to Pin1
Clamping Voltage (V)
7
6
5
4
3
2
1
0
2
4
6
8
10
12
14
16
18
20
22
24
Waveform
Parameter:
td = 8µs
tr = 20µs
Peak Pulse Current (A)
Revision 2014/12/03
© 2014-2015 Amazing Micro.
3
www.amazingIC.com
AZ6225-01F
Low Voltage Transient Voltage Suppressing Device
0402 DFN Package for ESD/Surge Protection
Applications Information
The AZ6225-01F is designed to protect one line
against System ESD/EFT/Lightning pulses by
clamping it to an acceptable reference. It
provides bi-directional protection.
The usage of the AZ6225-01F is shown in Fig. 1.
Protected line, such as data line, control line, or
power line, is connected at pin 1. The pin 2 is
connected to a ground plane on the board. In
order to minimize parasitic inductance in the
board traces, all path lengths connected to the
pins of AZ6225-01F should be kept as short as
possible.
In order to obtain enough suppression of ESD
induced transient, good circuit board is critical.
Thus, the following guidelines are recommended:
Minimize the path length between the
protected lines and the AZ6225-01F.
Place the AZ6225-01F near the input
terminals or connectors to restrict transient
coupling.
The ESD current return path to ground
should be kept as short as possible.
Use ground planes whenever possible.
NEVER route critical signals near board
edges and near the lines which the ESD
transient easily injects to.
Input
Output
V
BR
Transient
Voltage
-V
BR
V
BR
Normal
Operation
-V
BR
gnd
V
CL
gnd
-V
CL
gnd
gnd
Protected
Devices
1
1
AZ6225-01F
AZ5525-01F
AZ6225-01F
AZ5525-01F
Fig. 1
Revision 2014/12/03
© 2014-2015 Amazing Micro.
2
4
2
www.amazingIC.com
AZ6225-01F
Low Voltage Transient Voltage Suppressing Device
0402 DFN Package for ESD/Surge Protection
Fig. 2 shows another simplified example of using
AZ6225-01F to protect the control line, low speed
data line, and power line from ESD transient
stress.
VDD
Chip-B
1
Chip-A
Low Speed
Data Line
Chip-C
Control Line
AZ6225-01F
AZ5525-01F
2
AZ6225-01F
AZ5525-01F
AZ6225-01F
AZ5525-01F
Revision 2014/12/03
© 2014-2015 Amazing Micro.
1
2
Fig. 2
1
2
GND
5
www.amazingIC.com
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