AZ5A25-01F
Transient Voltage Suppressing Device
Tiny Pacakge for ESD/Transient Protection
Features
ESD Protect for 1 Line with Bi-directional
Provide ESD protection for the protected line to
IEC 61000-4-2 (ESD) ±15kV (air), ±13kV (contact)
IEC 61000-4-4 (EFT) 40A (5/50ns)
Cable Discharge Event (CDE)
proprietary clamping cell in a single package.
During transient conditions, the proprietary
clamping cell prevents over-voltage on the power
line or control/data lines, protecting any
downstream components.
AZ5A25-01F may be used to meet the ESD
immunity requirements of IEC 61000-4-2, Level 4
(±15kV air,
±8kV
contact discharge)
0201 small DFN package
saves board space
Protect one I/O line or one power line
Fast turn-on and Low clamping voltage
For low operating voltage applications: 5V
maximum
Solid-state silicon-avalanche and active circuit
triggering technology
Green Part
Circuit Diagram /
Pin Configuration
Applications
Mobile Phones
Hand Held Portable Applications
Computer Interfaces Protection
Microprocessors Protection
Serial and Parallel Ports Protection
Control Signal Lines Protection
Power lines on PCB Protection
Latchup Protection
1
2
DFN0603P2Y (Bottom View)
(0.6mm x 0.3mm x 0.3mm)
Description
AZ5A25-01F is a design which includes one
Bi-directional ESD rated clamping cell to protect
one power line, or one control line, or one low
speed data line in an electronic systems. The
AZ5A25-01F has been specifically designed to
protect sensitive components which are
connected to power and control lines from
over-voltage damage and latch-up caused by
Electrostatic Discharging (ESD), Electrical Fast
Transients (EFT), and Cable Discharge Event
(CDE).
AZ5A25-01F is a unique design which includes
Revision 2013/03/14
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AZ5A25-01F
Transient Voltage Suppressing Device
Tiny Pacakge for ESD/Transient Protection
SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Operating Supply Voltage
ESD per IEC 61000-4-2 (Air)
ESD per IEC 61000-4-2 (Contact)
Lead Soldering Temperature
Operating Temperature
Storage Temperature
T
SOL
T
OP
T
STO
PARAMETER
V
DC
V
ESD
RATING
±5.5
±15
±13
260 (10 sec.)
-55 to +85
-55 to +150
o
o
o
UNITS
V
kV
C
C
C
ELECTRICAL CHARACTERISTICS
PARAMETER
Stand-Off Voltage
Leakage Current
Breakdown
Voltage
ESD Clamping
Voltage
SYMBOL
V
RWM
I
Leak
T=25
o
C.
V
RWM
=
±5V,
T=25
o
C.
I
BV
= 1mA, T=25
o
C.
IEC 61000-4-2 +6kV, T=25
o
C, Contact
mode.
V
R
= 0V, f = 1MHz, T=25
o
C.
V
R
= 5V, f = 1MHz, T=25
o
C.
CONDITIONS
MINI
-5
TYP
MAX
5
1
UNITS
V
µA
V
BV
5.6
9
V
V
ESD_CL
C
IN-1
C
IN-2
14
5.5
3
7
4.5
V
pF
pF
Channel Input
Capacitance
Revision 2013/03/14
©2013 Amazing Micro.
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AZ5A25-01F
Transient Voltage Suppressing Device
Tiny Pacakge for ESD/Transient Protection
Typical Characteristics
8
7
Input Capacitance (pF)
6
Typical Variation of CIN vs. VIN
Pin-1 to Pin-2
5
4
3
2
1
0
-5
-4
-3
-2
-1
0
1
2
3
4
5
Input Voltage (V)
f = 1MHz, T=25 oC,
Transmission Line Pulsing (TLP) Current (A)
Transmission Line Pulsing (TLP) Measurement
18
16
14
12
10
8
6
4
2
0
-2
-4
-6
-8
-10
-12
-14
-16
-18
V_pulse
Pulse from a
transmission line
TLP_I
100ns
+
TLP_V
-
DUT
Pin-1 to Pin-2
-14 -12 -10 -8 -6 -4 -2
0
2
4
6
8 10 12 14
Transmission Line Pulsing (TLP) Voltage (V)
Revision 2013/03/14
©2013 Amazing Micro.
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AZ5A25-01F
Transient Voltage Suppressing Device
Tiny Pacakge for ESD/Transient Protection
Applications Information
The AZ5A25-01F is designed to protect one line
against
System
ESD/EFT/Cable-Discharge
pulses by clamping it to an acceptable reference.
It provides bi-directional protection.
The usage of the AZ5A25-01F is shown in Fig. 1.
Protected line, such as data line, control line, or
power line, is connected at pin 1. The pin 2 is
connected to a ground plane on the board. In
order to minimize parasitic inductance in the
board traces, all path lengths connected to the
pins of AZ5A25-01F should be kept as short as
possible.
In order to obtain enough suppression of ESD
induced transient, good circuit board is critical.
Thus, the following guidelines are recommended:
Minimize the path length between the
protected lines and the AZ5A25-01F.
Place the AZ5A25-01F near the input
terminals or connectors to restrict transient
coupling.
The ESD current return path to ground
should be kept as short as possible.
Use ground planes whenever possible.
NEVER route critical signals near board
edges and near the lines which the ESD
transient easily injects to.
Input
V
BR
Transient
Voltage
-V
BR
V
BR
Normal
Operation
-V
BR
gnd
gnd
V
CL
gnd
-V
CL
gnd
Output
AZ5A25-01F
AZ5A25-01F
1
2
1
2
Fig. 1
Revision 2013/03/14
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IC to be protected
AZ5A25-01F
Transient Voltage Suppressing Device
Tiny Pacakge for ESD/Transient Protection
Fig. 2 shows another simplified example of using
AZ5A25-01F to protect the control line, low
speed data line, and power line from ESD
transient stress.
VDD
Chip-B
Chip-A
Low Speed
Data Line
Control Line
Chip-C
2
AZ5A25-01F
2
2
AZ5A25-01F
1
1
GND
Fig. 2
Revision 2013/03/14
©2013 Amazing Micro.
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AZ5A25-01F
1
FPGA/CPLD
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