AGM – CPLD
AGM CPLD
DATASHEET
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AGM – CPLD
General Description
AGM CPLD family provides low-cost instant-on, non-volatile CPLDs, with densities from 256, 272 to 576 logic LUTs and
non-volatile flash storage of 256Kbits. The devices offer up to 144 I/O pins featuring with a user flash memory (UFM), and
in-system programming. The devices are designed to reduce cost and power while providing programmable solutions for a
wide range of applications.
Features
Low-Cost and low-power CPLD
Instant-on, non-volatile Compatible FPGA architecture.
Up to 4 global clock lines in the global clock network that drive throughout the entire device.
Provides programmable fast propagation delay and clock-to-output times.
Provides PLL per device provide clock multiplication and phaseshifting (AG256 has no PLL).
UFM supports non-volatile storage up to 256 Kbits.
Supports 3.3-V, 2.5-V, 1.8-V, and 1.5-V logic level
Programmable slew rate, drive strength, bus-hold, programmable pull-up resistors, open-drain output, Schmitt triggers
and programmable input delay.
Built-in Joint Test Action Group (JTAG) boundary-scan test (BST) circuitry complaint with IEEE Std. 1149.1-1990
ISP circuitry compliant with IEEE Std. 1532
3.3-V, 2.5-V, 1.8-V, 1.5-V LVCMOS and LVTTL standards
Emulated LVDS output (LVDS_E_3R)
Emulated RSDS output (RSDS_E_3R)
Operating junction temperature from -40 to 100
℃
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AGM – CPLD
Table 1-1 Shows AGM CPLD features
Feature
LUTs
UFM Size (bits)
Maximum User I/O pins
Operating junction temperature
AG256
256
256k
80
-40 to 100
℃
AG272
272
256k
80
-40 to 100
℃
AG576
576
256k
116
-40 to 100
℃
The AGM CPLDs are available in LQFP packages (refer to Table 1-2 AGM CPLD Packages and User I/O Pins).
Table 1-2 AGM CPLD Packages and User I/O Pins
Device
AGM256 / AG272
AGM576
100-Pin LQFP
80
80
144-in LQFP
-
116
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AGM – CPLD
Content
GENERAL DESCRIPTION
.............................................................................................................................................. 2
FEATURES
......................................................................................................................................................................... 2
CONTENT
.......................................................................................................................................................................... 4
1.
AGM ARCHITECTURE OVERVIEW
..................................................................................................................... 5
1.1.
1.2.
1.3.
1.4.
1.5.
1.6.
1.7.
1.8.
2.
F
UNCTIONAL
D
ESCRIPTION
.................................................................................................................................. 5
L
OGIC
A
RRAY
B
LOCKS
......................................................................................................................................... 5
L
OGIC
E
LEMENT
................................................................................................................................................... 5
F
LEX
T
RACK
I
NTERCONNECT
................................................................................................................................ 6
G
LOBAL
S
IGNALS
................................................................................................................................................. 6
P
HASE
L
OCKED
L
OOPS
(PLL
S
) ............................................................................................................................. 6
U
SER
F
LASH
M
EMORY
B
LOCK
............................................................................................................................. 8
I/O P
IN
S
TRUCTURE
.............................................................................................................................................. 8
JTAG AND IN-SYSTEM PROGRAMMING
........................................................................................................... 9
2.1.
2.2.
JTAG.................................................................................................................................................................... 9
I
N
-S
YSTEM
P
ROGRAMMING
.................................................................................................................................. 9
3.
POWER-ON RESET CIRCUITRY, ON-CHIP OSCILLATOR
........................................................................... 10
3.1.
3.2.
P
OWER
-O
N
R
ESET
C
IRCUITRY
............................................................................................................................ 10
O
N
-C
HIP
O
SCILLATOR
........................................................................................................................................ 10
4.
5.
6.
TIMING CHARACTERISTICS
.............................................................................................................................. 11
PIN-OUTS
................................................................................................................................................................ 12
REFERENCE AND ORDERING INFORMATION
.............................................................................................. 17
6.1.
6.2.
S
OFTWARE
.......................................................................................................................................................... 17
O
RDERING
I
NFORMATION
................................................................................................................................... 17
7.
REVISION HISTORY
.............................................................................................................................................. 17
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AGM – CPLD
1. AGM Architecture Overview
1.1. Functional Description
The AGM CPLD devices contain an industrial state-of-the art two-dimensional row- and column-based architecture to
implement custom logic. Column and row interconnects of varies speeds provide signal interconnects between logic blocks
(LBs) and IOs.
The logic array consists of LBs, with 16 logic slices (LS) in each LB. A slice is a small unit of logic providing efficient
implementation of user logic functions. LBs are grouped into rows and columns across the device. The CPLD devices’
density range is up to 576 slices.
The device global clock network consists of up to 4 global clock lines that drive through the entire device. The global clock
network can provide clocks for all resources within the device, such as input/output elements (IOEs), slices. The global
clock lines can also be used for other high fan-out signals.
Each device I/O pin is fed by an IOE located at the ends of LBrows and columns around the periphery of the device. I/O
pins support various single-ended standards. Each IOE contains a bidirectional I/O buffer.
Each device is embedded with a flash memory block. The big portion of this flash memory storage is used as dedicated
configuration flash memory (CFM) block. The CFM flash memory block provides the non-volatile storage for the all SRAM
configuration bits. The CFM automatically downloads and configures the logic blocks and IP during power-on, providing
instant-on sequence operation.
AGM CPLD device partitions 256k bits of flash memory as UFM (user flash memory) as general storage purposes. The
UFM provides programmable port connections to the logic array for reading and writing.
1.2. Logic Array Blocks
Each Logic Block consists of 16 slices, SLICE carry chains, SLICE control signals, a local interconnect, a look-up table
(LUT) chain, and register chain connection lines.
1.3. Logic Element
The smallest unit of logic in AGM architecture, the slice, is compact and provides advanced and flexible features with
efficient logic utilization. Each slice features:
A four-input look-up table (LUT4), which is a function generator that can implement any combinatorial logic function of
four inputs.
A programmable register
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