BJ8P509F
PRODUCT
SPECIFICATION
(V1.0)
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BJ8P509F
V1.0
Jul,2015
Contents
1.Features.............................................................................................................................................4
2. General Description.........................................................................................................................5
3. Block Diagram................................................................................................................................ 6
4. Pin connection and Pin descriptions............................................................................................... 6
4.1 Pin Assignments.................................................................................................................... 6
4.2 Pin descriptions..................................................................................................................... 7
5.memory organization........................................................................................................................7
5.1 Program Memory Organization......................................................................................... 7
5.2 Data Memory Organization................................................................................................8
6. Functional description................................................................................................................... 10
6.1 Operational Registers.......................................................................................................... 10
6.1.1 INDF (Indirect Addressing Register).......................................................................10
6.1.2 TMR0 (Time Clock/Counter register)..................................................................... 11
6.1.3 PCL (Low Bytes of Program Counter) & Stack...................................................... 11
6.1.4 STATUS (Status Register)....................................................................................... 13
6.1.5 FSR (Indirect Data Memory Address Pointer)........................................................ 14
6.1.6 PORTB (Port Data Register)....................................................................................14
6.1.7 PCON (Power Control Register)............................................................................. 14
6.1.8 WUCON (Port B Input Change Interrupt/Wake-up Control Register)................... 15
6.1.9 PCHBUF (High Byte Buffer of Program Counter)................................................. 15
6.1.10 PDCON (Pull-down Control Register)..................................................................15
6.1.11 ODCON (Open-drain Control Register)................................................................16
6.1.12 PHCON (Pull-high Control Register)....................................................................16
6.1.13 INTEN (Interrupt Mask Register)..........................................................................17
6.1.14 INTFLAG (Interrupt Status Register)................................................................... 18
6.1.15 ACC (Accumulator)............................................................................................... 18
6.1.16 OPTION Register...................................................................................................18
6.1.17 IOSTB (Port I/O Control Register)........................................................................19
6.2 I/O Port................................................................................................................................ 19
6.3 Timer0/WDT & pre-scaler............................................................................................... 21
6.3.1 Timer0...................................................................................................................... 21
6.3.1.1 Using Timer0 with an Internal Clock : Timer mode.....................................22
6.3.1.2 Using Timer0 with an External Clock : Counter mode................................ 22
6.3.2 Watchdog Timer (WDT).......................................................................................... 22
6.3.3 pre-scaler.................................................................................................................. 23
6.4 Interrupts............................................................................................................................. 24
6.4.1 External INT Interrupt............................................................................................. 24
6.4.2 Timer0 Interrupt....................................................................................................... 24
6.4.3 Port B Input Change Interrupt..................................................................................24
6.5 Power-down Mode (SLEEP).............................................................................................. 25
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BJ8P509F
V1.0
Jul,2015
6.5.1 Wake-up from SLEEP Mode....................................................................................25
6.6 Reset.................................................................................................................................... 26
6.6.1 Power-up Reset Timer(PWRT)................................................................................ 26
6.6.2 Oscillator Start-up Timer(OST)............................................................................... 27
6.6.3 Reset Sequence.........................................................................................................27
6.7 Hexadecimal Convert to Decimal (HCD)...........................................................................29
6.8 Oscillator Configurations....................................................................................................30
7. Absolute maximum....................................................................................................................... 34
8. Operating conditions.................................................................................................................. 34
9. Package Dimension....................................................................................................................... 35
9.1 8-PIN DIP............................................................................................................................35
9.2 8-PIN SOP...........................................................................................................................36
9.3 6-PIN SOT23.......................................................................................................................37
9.4 8-PIN TSSOP8.................................................................................................................... 38
10.Edition statement..........................................................................................................................39
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BJ8P509F
V1.0
Jul,2015
1.Features
Only 42 single word instructions
All instructions are single cycle except for program branches which are two-cycle
13-bit wide instructions
All OTP ROM area GOTO instruction
All OTP ROM area subroutine CALL instruction
8-bit
wide data path
5-level deep hardware stack
Operating speed: DC-20 MHz clock input
DC-100 ns instruction cycle
Device
BJ8P509FNB
BJ8P509FDB
BJ8P509FGA
BJ8P509FTB
Pins#
8
8
6
8
I/O#
6
6
4
6
OTP ROM(word)
1K
1K
1K
1K
Ram(Byte)
49
49
49
49
Direct, indirect addressing modes for data accessing
8-bit real time clock/counter (Timer0) with 8-bit programmable pre-scaler
Internal Power-on Reset (POR)
Built-in Low Voltage Detector (LVD) for Brown-out Reset (BOR)
Power-up Reset Timer (PWRT) and Oscillator Start-up Timer(OST)
On chip Watchdog Timer (WDT) with internal oscillator for reliable operation and
soft-ware watch-dog enable/disable control
One I/O port IOB with independent direction control
Soft-ware I/O pull-high/pull-down or open-drain control
One internal interrupt source: Timer0 overflow; Two external interrupt source: INT
pin, Port B input change
Wake-up from SLEEP by INT pin or Port B input change
Power saving SLEEP mode
Built-in 8MHz, 4MHz, 1MHz, and 455KHz internal RC oscillator
Programmable Code Protection
Built-in internal RC oscillator
Selectable oscillator options:
- ERC:
External Resistor/Capacitor Oscillator
- HF: High Frequency Crystal/Resonator Oscillator
- XT: Crystal/Resonator Oscillator
- LF: Low Frequency Crystal Oscillator
- IRC: Internal Resistor/Capacitor Oscillator
- ERIC: External Resistor/Internal Capacitor Oscillator
Wide-operating voltage range: 2.3V to 5.5V
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BJ8P509F
V1.0
Jul,2015
2.
General
Description
The BJ8P509F series is a family of low-cost, high speed, high noise immunity, OTP
ROM-based 8-bit CMOS Micro-controllers. It employs a RISC architecture with only 42
instructions. All instructions are single cycle except for program branches which take two
cycles. The easy to use and easy to remember instruction set reduces development
time significantly.
The BJ8P509F series consists of Power-on Reset (POR), Brown-out Reset (BOR),
Power-up Reset Timer (PWRT), Oscillator Start-up Timer(OST), Watchdog Timer, OTP
ROM, SRAM, tristate I/O port, I/O pull-high/open-drain/pull-down control, Power saving
SLEEP mode, real time programmable clock/counter, Interrupt, Wake-up from SLEEP
mode, and Code Protection for these products.
There are three oscillator
configurations to choose from, including the power-saving LP (Low Power) oscillator and
cost saving RC oscillator.
The BJ8P509F address 1K×13 of program memory.
The BJ8P509F can directly or indirectly address its register files and data memory.
All special function registers including the program counter are mapped in the data
memory.
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