SF1531S
η-Balance
TM
Current Mode PWM Controller
FEATURES
◆
Proprietary
η-Balance
Control to Boost
Light Load Efficiency
◆
Proprietary “Zero OCP/OPP Recovery Gap”
Control
◆
Built-in Soft Start Function
◆
Very Low Startup Current
◆
High Voltage CMOS Process with Excellent
ESD Protection
◆
Frequency Reduction and Burst Mode Control
for Energy Saving
◆
Current Mode Control
◆
Built-in Frequency Shuffling
◆
Programmable Switching Frequency
◆
Built-in Synchronous Slope Compensation
◆
Pins Floating Protection
◆
Cycle-by-Cycle Current Limiting
◆
Built-in Leading Edge Blanking (LEB)
◆
Constant Power Limiting
◆
Audio Noise Free Operation
◆
VDD OVP & Clamp
◆
VDD Under Voltage Lockout (UVLO)
TM
GENERAL DESCRIPTION
SF1531S is a high performance, high efficiency, low
cost, highly integrated current mode PWM controller
for offline flyback converter applications.
PWM switching frequency with shuffling is externally
programmable, which can reduce conduction EMI
emission of a power supply. When the output power
demands decrease, the IC decreases switching
TM
frequency based on the proprietary
η
-Balance
control to boost power conversion efficiency at the
light load. When the current set-point falls below a
given value, e.g. the output power demand
diminishes, the IC enters into burst mode and
provides excellent efficiency without audio noise.
SF1531S can achieve “Zero
OCP/OPP Recovery
Gap”
using SiFirst’s proprietary control algorithm.
Meanwhile, the OCP/OPP variation versus universal
line input is compensated.
The IC has built-in synchronized slope compensation
to prevent sub-harmonic oscillation at high PWM duty
output. The IC also has built-in soft start function to
soften the stress on the MOSFET during power on
period.
SF1531S integrates functions and protections of
Under Voltage Lockout (UVLO), VCC Over Voltage
Protection (OVP), Cycle-by-cycle Current Limiting
(OCP), All Pins Floating Protection, Over Load
Protection (OLP), RT Pin Short-to-GND Protection,
Gate Clamping, VCC Clamping, Leading Edge
Blanking (LEB).
SF1531S is available in SOT23-6, DIP-8 packages.
APPLICATIONS
Offline AC/DC Flyback Converter for
◆
AC/DC Adaptors
◆
Open-frame SMPS
◆
Set-Top Box Power Supplies
◆
ATX Standby Power
TYPICAL APPLICATION
DC Out
AC IN
6
GATE
5
VDD
4
CS
SF1531S
GND
FB
RT
1
2
3
TL431
©SiFirst Technology
-1-
Confidential
SiFirst_DS_1531S_V1.0
SF1531S
Block Diagram
Oscillator with
Frequency Shuffling
RT
Zero OCP Recovery
Gap Control
Frequency
Reduction Control
RT short/floating
protection
CS floating
protection
Trimmed Voltage &
Current Reference
LEB
Internal
blocks
OCP
VDD
POR
Soft start
5.5V
9V/14.5V
Slope
compensation
FB
VDD OVP
Burst Mode
Control
35V
28.5V
S
Q
R
Soft Gate
Driver
GATE
η-Balance
TM
Control
CS
GND
OLP
43ms Delay
3.7V
Pin Description
Pin Num
1
2
3
4
5
6
Pin Name
GND
FB
RT
CS
VDD
GATE
I/O
P
I
I
I
P
O
Description
Ground
Voltage feedback pin. The loop regulation is achieved by connecting a
photo-coupler to this pin. PWM duty cycle is determined by this pin voltage
and the current sense signal at Pin 3.
Set the switching frequency by connecting a resistor between RT and
GND. This pin has floating/short-to-GND protection.
Current sense input pin.
IC power supply pin.
Totem-pole gate driver output to drive the external MOSFET.
Absolute Maximum Ratings
(Note 1)
Parameter
VDD DC Supply Voltage
VCC DC Clamp Current
GATE pin
FB, RT, CS voltage range
Package Thermal Resistance (SOT-26)
Package Thermal Resistance (DIP-8)
Package Thermal Resistance (SOP-8)
Value
35
10
20
-0.3 to 7
250
90
150
Unit
V
mA
V
V
o
C/W
o
C/W
o
C/W
©SiFirst Technology
-3-
Confidential
SiFirst_DS_1531S_V1.0
SF1531S
Maximum Junction Temperature
Operating Temperature Range
Storage Temperature Range
Lead Temperature (Soldering, 10sec.)
ESD Capability, HBM (Human Body Model)
ESD Capability, MM (Machine Model)
150
-40 to 85
-65 to 150
260
3
250
C
C
o
C
o
C
kV
V
o
o
Recommended Operation Conditions
(Note 2)
Parameter
Supply Voltage, VDD
Operating Frequency
Operating Ambient Temperature
Value
11 to 25
50 to 130
-40 to 85
Unit
V
kHz
o
C
ELECTRICAL CHARACTERISTICS
(T
A
= 25
O
C, RT=100K ohm, VDD=18V, if not otherwise noted)
Symbol
Parameter
Supply Voltage Section (VDD Pin)
UVLO(ON)
UVLO(OFF)
I_Startup
I_VDD_Op
VDD_OVP
V
DD
_Clamp
T_Softstart
V
FB_
Open
I
FB
_Short
A
VCS
VFB_min_duty
V
TH
_PL
T
D
_PL
Z
FB
_IN
Vth_OC_min
T_blanking
T
D
_OC
VDD Under Voltage
Lockout Exit (Startup)
VDD Under Voltage
Lockout Enter
VDD Start up Current
Operation Current
VDD Over Voltage
Protection trigger
VDD Zener Clamp
Voltage
Soft Start Time
FB Open Voltage
FB short circuit
current
PWM Input Gain
FB under voltage gate
clock is off.
Power Limiting FB
Threshold Voltage
Power limiting
Debounce Time
Input Impedance
Internal current
limiting threshold
SENSE Input Leading
Edge Blanking Time
Over Current
Detection and Control
Delay
Normal Oscillation
Frequency
Operating RT Range
RT open voltage
Frequency shuffling
range
Frequency
Test Conditions
Min
14.5
8
Typ
15.5
9
5
Max
16.5
9.8
20
3.5
30
37.5
Unit
V
V
uA
mA
V
V
mSec
V
mA
V/V
V
V
mSec
Kohm
VDD =12.5V, Measure
current into VDD
V
FB
=3V,CL=1nF
26
I(V
DD
) = 10mA
33.5
2.5
28
35.5
3
5.5
Feedback Input Section(FB Pin)
Short FB pin to GND,
measure current
ΔV
FB
/ΔV
cs
1.05
2.0
1.0
3.6
Note 3
42
5
Zero duty cycle
0.70
0.75
250
CL=1nF at GATE,
90
0.80
Current Sense Input Section (CS Pin)
V
nSec
nSec
Oscillator Section (RT Pin)
F
OSC
RT_range
V_RT_open
∆F(shuffle)/Fosc
∆f_Temp
60
50
Note 4
-20
o
C to 100
o
C (Note 4)
-4
5
65
100
2.0
70
150
4
KHZ
Kohm
V
%
%
©SiFirst Technology
-4-
Confidential
SiFirst_DS_1531S_V1.0
SF1531S
∆f_VDD
Duty_max
F_BM
Temperature Stability
Frequency Voltage
Stability
Maximum Duty cycle
Burst Mode Base
Frequency
Output Low Level
Output High Level
Output Clamp Voltage
Level
Output Rising Time
Output Falling Time
VDD = 12-25V,
75
5
80
22
85
%
%
KHZ
Gate Drive Output (GATE Pin)
VOL
VOH
VG_Clamp
T_r
T_f
Io = 20 mA (sink)
Io = 20 mA (source)
VDD=24V
CL = 1nF
CL = 1nF
1
7.5
16
220
40
V
V
V
nSec
nSec
Note 1.
Stresses beyond those listed under
“Absolute
Maximum Ratings” may cause permanent damage to
the device. These are stress ratings only, and functional operation of the device at these or any other
conditions beyond those indicated in the operational sections of the specifications is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Note 2.
The device is not guaranteed to function outside its operating conditions.
Note 3.
The OLP debounce time is proportional to the period of switching cycle.
Note 4.
Guaranteed by design.
©SiFirst Technology
-5-
Confidential
SiFirst_DS_1531S_V1.0
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