SF5773S
2
nd
Generation Quasi-Resonant (
QR-II
FEATURES
◆
Easily Meet EPS Level 6
◆
AC Brownout Protection (BOP)
TM
◆
Proprietary
QR-II
Technology:
●Digital
Anti-jitter for Audio Noise Free
Operation
●
Digital Frequency Foldback
●
Digital Frequency Jittering for Better EMI
◆
Less than 100mW Standby Power
◆
Multi-Mode Operation for High Efficiency
◆
12.7us Maximum On Time
◆
80KHz Maximum Frequency Limit
◆
52KHz Frequency Low Clamping in QR Mode
◆
65% Maximum Duty Cycle
◆
Adaptive Slope Compensation for CCM Mode
◆
Built-in Soft Start Function
◆
Pin Floating Protection
◆
Built-in Synchronous Slope Compensation
◆
Cycle-by-Cycle Current Limiting
◆
Leading Edge Blanking (LEB)
◆
Constant Power Limiting
◆
VDD UVLO, OVP & Clamp
TM
) PWM Controller
with Brownout Protection
nd
GENERAL DESCRIPTION
APPLICATIONS
Offline AC/DC Flyback Converter for
◆
AC/DC Adaptors
◆
SMPS Power Supply
SF5773S is a high performance, 2 Generation
TM
Quasi-Resonant (QR-II ) PWM controller for offline
flyback power converter applications. The built-in
TM
technology with high level
proprietary
QR-II
protection features improves the SMPS reliability and
performance.
In SF5773S, the “Digital
Anti-Jitter”
function can
automatically select and lock a valley at a given
loading, which can achieve audio noise free
operation. On the other hand, the “Digital
Frequency
Jittering”
function makes the system have superior
EMI performance than conventional QR system.
SF5773S is a multi mode controller. When full
loadings, the IC works in CCM mode or QR mode
based on the AC line input. When the loading goes
low, the IC enters into “Digital
Frequency Foldback”
mode to boost power conversion efficiency. When the
output power is very small, the IC enters into burst
mode and can achieve less than 100mW no load
power.
SF5773S integrates functions and protections of
Under Voltage Lockout (UVLO), VCC Over Voltage
Protection (OVP), Output Over Voltage Protection
(Output OVP), Cycle-by-cycle Current Limiting (OCP),
Pin Floating Protection, Over Load Protection (OLP),
AC Brownout Protection, Soft Start, VCC Clamping,
Gate Clamping, etc. In SF5773S, the protection
functions are auto-recovery mode protection.
SF5773S is available in SOT23-6 package.
TYPICAL APPLICATION
AC IN
EMI
Filter
DC Out
SF5773S
1
2
3
GND
GATE
6
5
4
TL431
FB
VDD
DEM
CS
©SiFirst Technology
-1-
Confidential
SiFirst_DS_5773S_V1.0
SF5773S
Block Diagram
S
Q
R
DEM
DEM
3
Output OVP
Load OVP
Soft Gate
Driver
GATE
6
QR or CCM mode
AC Brownout
Protection
BOP
PWM/PFM,
Logic,
Timer
&
Fault
Management
Digital Frequency
Foldback
Burst Mode
4.7V
FB
2
Digital Frequency
Jittering
Adaptive Slope
compensation
Digital Anti-Jitter for
Valley Locking
Soft start
LEB
CS
4
VDD
5
9V/15V
POR
OCP &
Compensation
CS floating
protection
VDD OVP
OLP
35V
32V
82ms Delay
3.6V
1
GND
Absolute Maximum Ratings
(Note 1)
Parameter
VDD DC Supply Voltage
VCC DC Clamp Current
DEM Voltage Range
FB, CS Voltage Range
Package Thermal Resistance (SOT-26)
Maximum Junction Temperature
Operating Temperature Range
Storage Temperature Range
Lead Temperature (Soldering, 10sec.)
ESD Capability, HBM (Human Body Model)
ESD Capability, MM (Machine Model)
Value
35
10
-0.7 to 6
-0.3 to 7
250
150
-40 to 85
-65 to 150
260
3
250
Unit
V
mA
V
V
o
C/W
o
C
o
C
o
C
o
C
kV
V
Recommended Operation Conditions
(Note 2)
Parameter
Supply Voltage, VDD
Operating Ambient Temperature
Value
11 to 29
-40 to 85
Unit
o
V
C
©SiFirst Technology
-3-
Confidential
SiFirst_DS_5773S_V1.0
SF5773S
I
TH_
BOP_OFF
T
BOP
_PL
Brownout Turn-off trip
level
Brownout Debounce
Time
Sampling Time for
Digital Anti-jitter
Function
Maximum Number for
Valley Locking
Burst Mode Base
Frequency
Maximum Duty cycle
Frequency High
Clamp in QR Mode
Frequency
Low
Clamp in QR Mode
Frequency Jittering
range
Maximum ON Time
Maximum OFF Time
Minimum OFF Time
Output Low Level
Output High Level
Output Clamp Voltage
Level
Output Rising Time
Output Falling Time
72
Note 3
25
77
35
82
uA
mSec
Timer Section
T_counter
40
mSec
N_counter_max
F_BM
Duty_max
Fmax_QR_H
Fmin
_QR_L
∆F(jitter)/Fsw
Ton_max
Toff_max
Toff_min
VOL
VOH
VG_Clamp
T_r
T_f
8
22
Note 4
72
47
Note 4
-4
11.5
52
Note 4
Io = 20 mA (sink)
Io = 20 mA (source)
VDD=24V
GATE= 1nF
GATE= 1nF
12.7
57
2.5
65
80
52
88
57
4
14
64
KHz
%
KHz
KHz
%
us
us
uSec
V
V
V
nSec
nSec
Gate Drive Output (GATE Pin)
1
7.5
16
150
60
Note 1.
Stresses beyond those listed under
“Absolute
Maximum Ratings” may cause permanent damage to
the device. These are stress ratings only, and functional operation of the device at these or any other
conditions beyond those indicated in the operational sections of the specifications is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Note 2.
The device is not guaranteed to function outside its operating conditions.
Note 3.
The OLP debounce time is proportional to the period of switching cycle.
Note 4.
Guaranteed by design.
©SiFirst Technology
-5-
Confidential
SiFirst_DS_5773S_V1.0
工作这点儿事
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
