η-Balance
TM
Current Mode PWM Controller
FEATURES
◆
Less than 75mW Standby Power
◆
Programmable OLP Debounce Time
◆
Proprietary
η-Balance
TM
Control to Boost
Light Load Efficiency
◆
Proprietary “Zero OCP/OPP Recovery Gap”
Control
◆
Proprietary
“Audio
Noise
Free
OCP
Compensation”
◆
Dmax up to 80%
◆
Fixed 65KHz Switching Frequency
◆
Built-in Frequency Shuffling
◆
Built-in Soft Start Function
◆
Frequency Reduction and Burst Mode Control
for Energy Saving
◆
Built-in Synchronous Slope Compensation
◆
Cycle-by-Cycle Current Limiting
◆
Built-in Leading Edge Blanking (LEB)
◆
Current Mode Control
◆
Pin Floating Protection
◆
Very Low Startup Current
◆
Audio Noise Free Operation
◆
VDD UVLO, OVP & Clamp
SF5533W
W
GENERAL DESCRIPTION
SF5533W is a high performance, high efficiency,
highly integrated current mode PWM controller for
offline flyback converter applications. The OLP
debounce time can be programmed in SF5533W.
In SF5533W, PWM switching frequency with shuffling
is fixed 65KHz and is trimmed to tight range. When
the output power demands decrease, the IC
decreases switching frequency based on the
proprietary
η
-Balance
TM
control to boost power
conversion efficiency at the light load. When output
power falls below a given value, the IC enters into
burst mode and can achieve less than 75mW no load
power.
The IC can achieve “Zero
OCP/OPP Recovery Gap”
using SiFirst’s proprietary control algorithm.
SF5533W also has built in proprietary “Audio
Noise
Free OCP Compensation”,
which can achieve
constant power limiting and can achieve audio noise
operation at heavy loading when line input is around
90VAC.
SF5533W integrates functions and protections of
Under Voltage Lockout (UVLO), VDD Over Voltage
Protection (OVP), Cycle-by-cycle Current Limiting
(OCP), Pins Floating Protection, Over Load
Protection (OLP), Gate Clamping, RT Pin Short-to-
GND Protection, VDD Clamping, Leading Edge
Blanking (LEB), Soft Start, etc.
SF5533W is available in SOT23-6 package.
APPLICATIONS
Offline AC/DC Flyback Converter for
◆
AC/DC Adaptors
◆
Open-frame SMPS
◆
Laptop Charger
TYPICAL APPLICATION
DC Out
AC IN
6
GATE
5
VDD
4
CS
SF5533
GND
FB
CT
1
2
3
TL431
Optional
©SiFirst Technology
-1-
Confidential
SiFirst_DS_5533_V1.0
SF5533W
W
Block Diagram
65KHz Oscillator with
Frequency Shuffling
S
Q
R
Totem Pole
Gate Driver
GATE
6
1
GND
Zero OCP Recovery
Gap Control
Frequency
Reduction Control
η-Balance
TM
Control
Trimmed Voltage &
Current Reference
Internal
blocks
CS floating
protection
LEB
CS
4
VDD
5
POR
VDD OVP
9V/15.5V
PWM
&
Logic
OCP
Soft start
4.5V
Slope
compensation
FB
2
Burst Mode
Control
35V
27V
OLP
14uA
3.7V
CT
3
55ms Delay
3V
Pin Description
Pin Num
1
2
Pin Name
GND
FB
I/O
P
I
Description
Ground
Voltage feedback pin. The loop regulation is achieved by connecting a
photo-coupler to this pin. PWM duty cycle is determined by this pin voltage
and the current sense signal at Pin 4.
Pin for program OLP debounce time. If this pin is floating, the OLP time is
55ms. If an external capacitor is connected between CT and GND, the
OLPdebounce time can be programmable.
Current sense input pin.
IC power supply pin.
Totem-pole gate driver output to drive the external MOSFET.
3
CT
I
4
5
6
CS
VDD
GATE
I
P
O
©SiFirst Technology
-3-
Confidential
SiFirst_DS_5533_V1.0
Absolute Maximum Ratings
(Note 1)
Parameter
VDD DC Supply Voltage
VDD DC Clamp Current
GATE pin
FB, CT, CS voltage range
Package Thermal Resistance (SOT23-6)
Maximum Junction Temperature
Operating Temperature Range
Storage Temperature Range
Lead Temperature (Soldering, 10sec.)
ESD Capability, HBM (Human Body Model)
ESD Capability, MM (Machine Model)
θ½a
θ½c
SF5533W
W
Value
35
10
20
-0.3 to 7
250
70
150
-40 to 85
-65 to 150
260
3
250
Unit
V
mA
V
V
o
C/W
o
C
o
C
o
C
o
C
kV
V
Recommended Operation Conditions
(Note 2)
Parameter
Value
Unit
Supply Voltage, VDD
10 to 25
V
Operating Frequency
50 to 130
kHz
o
C
Operating Ambient Temperature
-40 to 85
Note 1.
Stresses beyond those listed under
“Absolute
Maximum Ratings” may cause permanent damage to
the device. These are stress ratings only, and functional operation of the device at these or any other
conditions beyond those indicated in the operational sections of the specifications is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Note 2.
The device is not guaranteed to function outside its operating conditions.
©SiFirst Technology
-4-
Confidential
SiFirst_DS_5533_V1.0
SF5533W
W
ELECTRICAL CHARACTERISTICS
(T
A
= 25
O
C, RT=100K ohm, VDD=18V, if not otherwise noted)
Symbol
Parameter
Supply Voltage Section (VDD Pin)
UVLO(ON)
UVLO(OFF)
I_Startup
I_VDD_Op
VDD_OVP
V
DD
_Clamp
T_Softstart
V
FB_
Open
I
FB
_Short
A
VCS
VFB_min_duty
V
TH
_PL
T
D
_PL
Z
FB
_IN
Vth_OC_min
Vth_OC_max
T_blanking
T
D
_OC
VDD Under Voltage
Lockout Exit (Startup)
VDD Under Voltage
Lockout Enter
VDD Start up Current
Operation Current
VDD Over Voltage
Protection trigger
VDD Zener Clamp Voltage
Soft Start Time
FB Open Voltage
FB short circuit current
PWM Input Gain
FB under voltage gate
clock is off.
Power Limiting FB
Threshold Voltage
Power limiting Debounce
Time
Input Impedance
Internal current limiting
threshold
Internal current limiting
threshold
SENSE Input Leading
Edge Blanking Time
Over Current Detection
and Control Delay
Normal Oscillation
Frequency
Frequency shuffling range
Frequency Temperature
Stability
Frequency Voltage
Stability
Maximum Duty cycle
Burst Mode Base
Frequency
Output Current of CT Pin
Comparator threshold for
OLP debounce time
Test Conditions
Min
14.5
8
Typ
15.5
9
5
2.0
27
Max
16.5
10
20
3.5
Unit
V
V
uA
mA
V
V
mSec
VDD =12.5V
V
FB
=3V,CL=1nF
I(V
DD
) = 10 mA
35.5
4
4.1
4.5
0.33
1.6
1.0
3.7
5
Feedback Input Section(FB Pin)
Short FB pin to GND
ΔV
FB
/ΔV
cs
V
mA
V/V
V
V
mSec
Kohm
0.80
V
V
nSec
nSec
Note 3
55
14
Current Sense Input Section (CS Pin)
Zero duty cycle
0.70
0.75
1.0
250
CL=1nF at GATE,
65
Oscillator Section
F
OSC
∆F(shuffle)/Fosc
∆f_Temp
∆f_VDD
Duty_max
F_BM
I_CT
V
TH
_CT
VOL
VOH
60
Note 4
-20
o
C to 100
o
C (Note 4)
VDD = 12-25V,
75
-4
5
5
80
22
10
14
3
1
16
150
60
18
85
65
70
4
KHz
%
%
%
%
KHz
uA
V
V
V
V
nSec
nSec
OLP Debounce Program Section (CT Pin)
Gate Drive Output (GATE Pin)
Output Low Level
Io = 20 mA (sink)
Output High Level
Io = 20 mA (source)
7.5
Output Clamp Voltage
VG_Clamp
VDD=24V
Level
T_r
Output Rising Time
CL = 1nF
T_f
Output Falling Time
CL = 1nF
Note 3.
The OLP debounce time is proportional to the period of switching cycle.
Note 4.
Guaranteed by design.
©SiFirst Technology
-5-
Confidential
SiFirst_DS_5533_V1.0
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