SF5877
HV-mW
TM
、
2
nd
Generation Quasi-Resonant (
QR-II
TM
) PWM Controller
FEATURES
◆
Easily Meet EPS Level 6
TM
◆
Proprietary
QR-II
Technology:
●Digital Anti-jitter for Audio Noise Free
Operation
● Digital Frequency Foldback
● Digital Frequency Jittering
TM
◆
Proprietary
HV-mW
to Achieve Less than
50mW Standby Power
◆
Multi-Mode Operation for High Efficiency
◆
12.7us Maximum On Time
◆
80KHz Maximum Frequency Limit
◆
53KHz Frequency Low Clamping in QR Mode
◆
Maximum 65% Duty Cycle
◆
Adaptive Slope Compensation for CCM Mode
◆
Latch Plug-off Protection
◆
Built-in Soft Start Function
◆
Pin Floating Protection
◆
Built-in Synchronous Slope Compensation
◆
Cycle-by-Cycle Current Limiting
◆
Leading Edge Blanking (LEB)
◆
Constant Power Limiting
◆
VDD UVLO, OVP & Clamp
GENERAL DESCRIPTION
APPLICATIONS
Offline AC/DC Flyback Converter for
◆
AC/DC Adaptors
◆
SMPS Power Supply
SF5877 is a high performance, 2 Generation Quasi-
TM
Resonant (QR-II ) PWM controller for offline flyback
power converter applications. The built-in proprietary
HV-mW
TM
technology and
QR-II
TM
technology with
high level protection features can improve the SMPS
reliability and performance.
In SF5877, the “Digital
Anti-Jitter”
function can
automatically select and lock a valley at a given
loading, which can achieve audio noise free
operation. On the other hand, the “Digital
Frequency
Jittering”
function makes the system have superior
EMI performance than conventional QR system.
SF5877 is a multi mode controller. When full loadings,
the IC works in CCM mode or QR mode based on the
AC line input. When the loading goes low, the IC
enters into “Digital
Frequency Foldback”
mode to
boost power conversion efficiency. When the output
power is very small, the IC enters into burst mode
and can achieve less than 50mW no load power.
SF5877 integrates functions and protections of Under
Voltage Lockout (UVLO), VDD Over Voltage
Protection (VDD OVP), Output Over Voltage
Protection (Output OVP), Cycle-by-cycle Current
Limiting (OCP), Pin Floating Protection, Over Load
Protection (OLP), Soft Start, VCC Clamping, Gate
Clamping, etc. In SF5877, VDD OVP and Output
OVP are latch mode protections, the other
protections are auto-recovery mode.
SF5877 is available in SOP8 package.
nd
TYPICAL APPLICATION
EMI
Filter
SF5877
1 DEM
2
3
FB
CS
HV 8
NC 7
VDD 6
GATE 5
TL431
4 GND
©SiFirst Technology
-1-
Confidential
SiFirst_DS_5877_V1.0
SF5877
Block Diagram
S
Q
R
DEM
DEM
1
Output OVP
Load OVP
Soft Gate
Driver
GATE
5
QR or CCM mode
Digital Frequency
Jittering
PWM/PFM,
Logic,
Timer
&
Fault
Management
Digital Frequency
Foldback
Burst Mode
4.5V
Digital Anti-Jitter for
Valley Locking
HV
8
FB
2
Adaptive Slope
compensation
POR
VDD
6
15V/9V
HV Latch
CS floating
protection
Soft start
LEB
OCP &
Compensation
CS
3
VDD OVP
OLP
35V
32V
75ms Delay
3.6V
1
GND
Absolute Maximum Ratings
(Note 1)
Parameter
HV Voltage range
VDD DC Supply Voltage
VDD DC Clamp Current
DEM Voltage Range
FB, CS Voltage Range
Package Thermal Resistance (SOP-8)
Maximum Junction Temperature
Operating Temperature Range
Storage Temperature Range
Lead Temperature (Soldering, 10sec.)
ESD Capability, HBM (Human Body Model) (Except HV Pin)
ESD Capability, MM (Machine Model)
Value
-0.3 to 700
35
10
-0.7 to 6
-0.3 to 7
150
150
-40 to 85
-65 to 150
260
3
250
Unit
V
V
mA
V
V
o
C/W
o
C
o
C
o
C
o
C
kV
V
Recommended Operation Conditions
(Note 2)
Parameter
Supply Voltage, VDD
Operating Ambient Temperature
Value
11 to 29
-40 to 85
Unit
o
V
C
©SiFirst Technology
-3-
Confidential
SiFirst_DS_5877_V1.0
SF5877
T
DEM_OUT
start of secondary
stroke
Timeout after last
demag transition
Sampling Time for
Digital Anti-jitter
Function
Maximum Number for
Valley Locking
Burst Mode Base
Frequency
Maximum Duty cycle
Frequency high clamp
in QR mode
Frequency low clamp
in QR mode
Frequency shuffling
range
Maximum on time
Maximum off time
Minimum OFF time
VDD latch mode high
voltage
VDD Latch Release
Voltage
VDD Current when
latch off
Output Low Level
Output High Level
Output Clamp Voltage
Level
Output Rising Time
Output Falling Time
Note 4
5
uSec
Timer Section
T_counter
40
mSec
N_counter_max
F_BM
Duty_max
Fmax_QR_H
Fmin
_QR_L
∆F(shuffle)/Fosc
Ton_max
Toff_max
Toff_min
8
22
65
72
47
Note 4
-4
11.5
52
Note 3
12.7
57
2.5
12
8.7
VDD= V
Latch_
release+1V
100
80
52
88
57
4
14
64
KHz
%
KHz
KHz
%
us
us
uSec
V
V
uA
Latch Protection
VDD_latch_H
V
Latch_
release
Ivdd(latch)
Gate Drive Output (GATE Pin)
VOL
VOH
VG_Clamp
T_r
T_f
Io = 20 mA (sink)
Io = 20 mA (source)
VDD=24V
GATE= 1nF
GATE= 1nF
0.3
11
16
80
40
V
V
V
nSec
nSec
Note 1.
Stresses beyond those listed under
“Absolute
Maximum Ratings” may cause permanent damage to
the device. These are stress ratings only, and functional operation of the device at these or any other
conditions beyond those indicated in the operational sections of the specifications is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Note 2.
The device is not guaranteed to function outside its operating conditions.
Note 3.
The OLP debounce time is proportional to the period of switching cycle.
Note 4.
Guaranteed by design.
©SiFirst Technology
-5-
Confidential
SiFirst_DS_5877_V1.0
DSP 与 ARM 处理器
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
