SF5887
2
nd
Generation Quasi-Resonant (
QR-II
FEATURES
◆
Meet EPS Level 6
TM
◆
Proprietary
QR-II
Technology:
●Digital Anti-jitter for Audio Noise Free
Operation
● Digital Frequency Foldback
● Digital Frequency Jittering for Better EMI
◆
Programmable Over Temperature Protection
(OTP)
◆
Multi-Mode Operation for High Efficiency
◆
12.7us Maximum On Time
◆
80KHz Maximum Frequency Limit
◆
52KHz Frequency Low Clamping in QR Mode
◆
65% Maximum Duty Cycle
◆
Adaptive Slope Compensation for CCM Mode
◆
Built-in Soft Start Function
◆
Pin Floating Protection
◆
Built-in Synchronous Slope Compensation
◆
Cycle-by-Cycle Current Limiting
◆
Leading Edge Blanking (LEB)
◆
Constant Power Limiting
◆
VDD UVLO, OVP & Clamp
TM
) PWM Controller
OTP Protection
nd
GENERAL DESCRIPTION
APPLICATIONS
Offline AC/DC Flyback Converter for
◆
AC/DC Adaptors
◆
SMPS Power Supply
SF5887 is a high performance, 2 Generation Quasi-
TM
Resonant (QR-II ) PWM controller for offline flyback
power converter applications. The built-in proprietary
QR-II
TM
technology with high level protection
features improves the SMPS reliability and
performance.
In SF5887, the “Digital
Anti-Jitter”
function can
automatically select and lock a valley at a given
loading, which can achieve audio noise free
operation. On the other hand, the “Digital
Frequency
Jittering”
function makes the system have superior
EMI performance than conventional QR system.
SF5887 is a multi mode controller. When full loadings,
the IC works in CCM mode or QR mode based on the
AC line input. When the loading goes low, the IC
enters into “Digital
Frequency Foldback”
mode to
boost power conversion efficiency. When the output
power is very small, the IC enters into burst mode
and provides excellent efficiency without audio noise.
SF5887 integrates functions and protections of Under
Voltage Lockout (UVLO), VCC Over Voltage
Protection (OVP), Output Over Voltage Protection
(Output OVP), Programmable Over Temperature
Protection (OTP), Cycle-by-cycle Current Limiting
(OCP), Pin Floating Protection, Over Load Protection
(OLP), Soft Start, VCC Clamping, Gate Clamping, etc.
In SF5887, the protection functions are auto-recovery
mode protection.
SF5887 is available in SOP8 package.
TYPICAL APPLICATION
AC IN
EMI
Filter
DC Out
SF5887
20K
NTC
1 RI
2 FB
3 CS
4 GND
RT 8
DEM 7
VCC 6
GATE 5
TL431
©SiFirst Technology
-1-
Confidential
SiFirst_DS_5887_V1.0
SF5887
Pin Configuration
RI
FB
CS
GND
1
2
3
4
SOP8
8
7
6
5
RT
DEM
VCC
GATE
Ordering Information
Part Number
SF5887SG
SF5887SGT
Top Mark
SF5887SG
SF5887SG
SOP8
SOP8
Package
Green
Green
Tape & Reel
Yes
Marking Information
SF5887SG
Y WW
YWW: Year&Week code
Pin Description
Pin Num
1
Pin Name
RI
I/O
I
Description
Set the internal frequency and timer by connecting a resistor between RI
and GND. The resistor is recommended to be set in the vicinity of 20K
Ohm.
Voltage feedback pin. The loop regulation is achieved by connecting a
photo-coupler to this pin. PWM duty cycle is generated by this pin voltage
and the current sense signal at Pin 3.
Current sense input pin.
IC ground pin.
Totem-pole gate driver output to drive the external MOSFET.
IC power supply pin.
Transformer core demagnetization detection pin. This pin is also used for
output over voltage protection (Output OVP).
This pin is for over temperature protection by connecting an external NTC
resistor to ground. Once the pin voltage drops below a fixed limit of 1.05V,
PWM output will be disabled.
2
FB
I
3
4
5
6
7
8
CS
GND
GATE
VCC
DEM
RT
I
P
O
P
I
I
©SiFirst Technology
-2-
Confidential
SiFirst_DS_5887_V1.0
SF5887
Block Diagram
Digital Frequency
Jittering
Digital Anti-Jitter for
Valley Locking
DEM
DEM
7
Output OVP
Load OVP
S
Q
R
Soft Gate
Driver
GATE
5
QR or CCM mode
RI
1
Trimmed Current
Source
Digital Frequency
Foldback
Burst Mode
4.7V
100uA
RT
8
OTP
PWM/PFM,
Logic,
Timer
&
Fault
Management
FB
2
Adaptive Slope
compensation
1.05V
Soft start
LEB
POR
CS
3
VDD
6
9V/15V
OCP &
Compensation
CS floating
protection
VDD OVP
OLP
35V
32V
82ms Delay
3.6V
4
GND
Absolute Maximum Ratings
(Note 1)
Parameter
VDD DC Supply Voltage
VCC DC Clamp Current
DEM Voltage Range
FB, CS, RI, RT Voltage Range
Package Thermal Resistance (SOP-8)
Maximum Junction Temperature
Operating Temperature Range
Storage Temperature Range
Lead Temperature (Soldering, 10sec.)
ESD Capability, HBM (Human Body Model)
ESD Capability, MM (Machine Model)
Value
35
10
-0.7 to 6
-0.3 to 7
150
150
-40 to 85
-65 to 150
260
3
250
Unit
V
mA
V
V
o
C/W
o
C
o
C
o
C
o
C
kV
V
Recommended Operation Conditions
(Note 2)
Parameter
Supply Voltage, VDD
Operating Ambient Temperature
Value
11 to 29
-40 to 85
Unit
o
V
C
©SiFirst Technology
-3-
Confidential
SiFirst_DS_5887_V1.0
SF5887
N_counter_max
F_BM
Duty_max
Fmax_QR_H
Fmin
_QR_L
∆F(jitter)/Fsw
Ton_max
Toff_max
Toff_min
I_RT
V
TH_
OTP
V
TH_
OTP
_
OFF
V
TH_
OTP
_
Hys
V_RI
RI
VOL
VOH
VG_Clamp
T_r
T_f
Digital Anti-jitter
Function
Maximum Number for
Valley Locking
Burst Mode Base
Frequency
Maximum Duty cycle
Frequency High
Clamp in QR Mode
Frequency
Low
Clamp in QR Mode
Frequency Jittering
range
Maximum ON Time
Maximum OFF Time
Minimum OFF Time
Output Current of RT
Pin
OTP
Threshold
Voltage
OTP Release Voltage
OTP Hysteresis
RI Pin Voltage
RI Resistor
Output Low Level
Output High Level
Output Clamp Voltage
Level
Output Rising Time
Output Falling Time
Io = 20 mA (sink)
Io = 20 mA (source)
VDD=24V
GATE= 1nF
GATE= 1nF
8
22
Note 4
72
47
Note 4
-4
11.5
52
Note 4
12.7
57
2.5
100
1.00
1.05
1.1
0.1
2.0
20K
1.10
65
80
52
88
57
4
14
64
KHz
%
KHz
KHz
%
us
us
uSec
uA
V
V
V
V
Ohm
V
V
V
nSec
nSec
Over Temperature Protection (RT Pin)
Trimmed Reference (RI Pin)
18K
22K
1
7.5
16
150
60
Gate Drive Output (GATE Pin)
Note 1.
Stresses beyond those listed under
“Absolute
Maximum Ratings” may cause permanent damage to
the device. These are stress ratings only, and functional operation of the device at these or any other
conditions beyond those indicated in the operational sections of the specifications is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Note 2.
The device is not guaranteed to function outside its operating conditions.
Note 3.
The OLP debounce time is proportional to the period of switching cycle.
Note 4.
Guaranteed by design.
©SiFirst Technology
-5-
Confidential
SiFirst_DS_5887_V1.0
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