SF1560
Highly Integrated Current Mode PWM Controller
FEATURES
◆
Latch Plug-off Protection with External
Triggering
◆
Built-in Soft Start Function
◆
Very Low Startup Current
◆
Frequency Reduction and Burst Mode Control
for Energy Saving
◆
Built-in Frequency Shuffling
◆
Programmable Switching Frequency
◆
Built-in Synchronous Slope Compensation
◆
Cycle-by-Cycle Current Limiting
◆
All Pins Floating Protection
◆
High Voltage CMOS Process with Excellent
ESD Protection
◆
Current Mode Control
◆
Built-in Leading Edge Blanking (LEB)
◆
Constant Power Limiting
◆
Audio Noise Free Operation
◆
VDD OVP & Clamp
◆
VDD Under Voltage Lockout (UVLO)
with Latch
GENERAL DESCRIPTION
SF1560 is a high performance, highly integrated
current mode PWM controller for medium to large
offline flyback converter applications.
In SF1560, the PWM switching is internally trimmed
to tight range. To improve EMI performance, the IC
integrates frequency shuffling function to reduce
conduction EMI emission of a power supply. The IC
also integrates Constant Power Limiting block to
achieve constant output power limit from 90VAC to
264VAC.
Under light load conditions, a green mode function
can continuously decrease the switching frequency.
Under zero-load conditions, the power supply enters
into burst mode and provides excellent efficiency
without audio noise generated. This green mode
function enables power supplies to meet international
power conservation requirements.
SF1560 integrates functions and protections of Under
Voltage Lockout (UVLO), VDD Over Voltage
Protection (OVP), Soft Start, External Programmable
Over Temperature Protection (OTP), Cycle-by-cycle
Current Limiting (OCP), Over Load Protection (OLP),
All Pins Floating Protection, RI Pin Short-to-GND
Protection, GATE Clamping, VDD Clamping, Leading
Edge Blanking (LEB).
In SF1560, the OTP and VDD OVP is latch plug-off
protection. The other protection functions are auto-
recovery mode protection.
SF1560 is available in SOP-8 and DIP-8 packages.
APPLICATIONS
Offline AC/DC Flyback Converter for
◆
AC/DC Power Adaptors
◆
Open-frame SMPS
◆
Print Power, Scanners, and Motor Drivers
TYPICAL APPLICATION
AC IN
EMI
Filter
DC Out
SF1560
1
2
3
4
GND
GATE
8
7
6
NTC
FB
VDD
VIN
CS
TL431
RI
RT
5
©SiFirst Technology
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Confidential
SiFirst_DS_1560_V1.1
SF1560
Block Diagram
RI
4
RI short/floating
protection
Trimmed Voltage &
Current Reference
S
SET
Soft Gate
Driver
Q
GATE
8
R
CLR
Q
Green Mode
operation
OSC
Frequency Shuffling
VIN
3
LEB
CS
6
POR
VDD
7
OVP
33V
25V
UVLO
PWM
&
Logic
OCP
& Compensation
Slope
compensation
5.9V
CS Floating
Protection
GND
1
70uA
RT
5
HV Latch
Soft start
FB
2
OTP
OLP
Burst Mode
Control
4.4V
82ms Delay
1.065V
Pin Description
Pin Num
1
2
Pin Name
GND
FB
I/O
P
I
Description
IC ground pin.
Voltage feedback pin. The loop regulation is achieved by connecting a
photo-coupler to this pin. PWM duty cycle is generated by this pin voltage
and the current sense signal at Pin 6.
This pin is connected to the rectified line input via a large value resistor.
The function of the pin is for startup and line voltage sensing.
Set the switching frequency by connecting a resistor between RI and
GND. This pin has floating/short-to-GND protection.
This pin is for over temperature protection by connecting an external NTC
resistor to ground. Once the pin voltage drops below a fixed limit of
1.065V, PWM output will be disabled.
Current sense input pin.
IC power supply pin.
Totem-pole gate driver output to drive the external MOSFET.
3
4
5
VIN
RI
RT
I
I
I
6
7
6
CS
VDD
GATE
I
P
O
Absolute Maximum Ratings
(Note 1)
Parameter
VDD/VIN DC Supply Voltage
VDD DC Clamp Current
Value
33
10
Unit
V
mA
©SiFirst Technology
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Confidential
SiFirst_DS_1560_V1.1
SF1560
GATE pin
FB, RI, RT, CS voltage range
Package Thermal Resistance (DIP-8)
Package Thermal Resistance (SOP-8)
Maximum Junction Temperature
Operating Temperature Range
Storage Temperature Range
Lead Temperature (Soldering, 10sec.)
ESD Capability, HBM (Human Body Model)
ESD Capability, MM (Machine Model)
20
-0.3 to 7
90
150
150
-40 to 85
-65 to 150
260
3
250
V
V
o
C/W
o
C/W
o
C
o
C
o
C
o
C
kV
V
Recommended Operation Conditions
(Note 2)
Parameter
Supply Voltage, VDD
Operating Frequency
Operating Ambient Temperature
Value
11 to 23
50 to 130
-40 to 85
Unit
V
kHz
o
C
ELECTRICAL CHARACTERISTICS
(T
A
= 25 C, RI=24K ohm, VDD=18V, if not otherwise noted)
O
Symbol
Parameter
Supply Voltage Section (VDD Pin)
I_Startup
I_VDD_Op
UVLO(ON)
UVLO(OFF)
VDD_OVP_ON
VDD_OVP_Hys
V
DD
_Clamp
T_Softstart
VDD Start up Current
Operation Current
VDD Under Voltage
Lockout Exit (Startup)
VDD Under Voltage
Lockout Enter
VDD Over Voltage
Protection trigger
VDD OVP Hysteresis
VDD Zener Clamp
Voltage
System Soft Start
Time
PWM Input Gain
FB Open Voltage
FB short circuit
current
FB under voltage gate
clock is off.
Power Limiting FB
Threshold Voltage
Power limiting
Debounce Time
Input Impedance
SENSE Input Leading
Edge Blanking Time
Internal current
limiting threshold
Over Current
Detection and Control
Delay
Normal Oscillation
Test Conditions
VDD =15V, Measure
current into VDD
V
FB
=3V,GATE=1nF
Min
Typ
5
2.5
16.5
10.5
25
2
33
3
Max
20
3.5
17.5
11.5
26.5
Unit
uA
mA
V
V
V
V
V
mSec
15.5
9.5
23.5
I(V
DD
) = 5mA
Feedback Input Section(FB Pin)
A
VCS
V
FB_
Open
I
FB
_Short
VFB_min_duty
V
TH
_PL
T
D
_PL
Z
FB
_IN
T_blanking
Vth_OC_max
T
D
_OC
ΔV
FB
/ΔV
cs
2.8
5.9
1.2
1.0
4.4
Note 3
82
5
250
I(VIN)=0
GATE=1nF
0.85
0.9
120
0.95
V/V
V
mA
V
V
mSec
Kohm
nSec
V
nSec
Short FB pin to GND,
measure current
Current Sense Input Section (CS Pin)
Oscillator Section (RI Pin)
F
OSC
60
65
70
KHZ
©SiFirst Technology
-4-
Confidential
SiFirst_DS_1560_V1.1
SF1560
∆F(shuffle)/Fosc
∆f_Temp
∆f_VDD
Duty_max
RI_range
V_RI_open
F_BM
Frequency
Frequency shuffling
range
Frequency
Temperature Stability
Frequency Voltage
Stability
Maximum Duty cycle
Operating RI Range
RI open voltage
Burst Mode Base
Frequency
Output Current of RT
Pin
OTP
Threshold
Voltage
OTP Release Voltage
OTP Hysteresis
RT Pin Open Voltage
VDD Latch Release
Voltage
VDD Current when
latch off
Output Low Level
Output High Level
Output Clamp Voltage
Level
Output Rising Time
Output Falling Time
Note 4
-40 C to 125 C (Note 4)
VDD = 12-23V (Note 4)
75
12
o
o
-4
5
5
80
24
2.0
22
4
%
%
%
85
60
%
Kohm
V
KHz
Over Temperature Protection (RT Pin)
I_RT
V
TH_
OTP
V
TH_
OTP
_
OFF
V
TH_
OTP
_
Hys
V_RT_Open
70
1.015
1.065
1.165
0.1
4.6
5.5
VDD= V
Latch_
release+1V
6
40
6.5
1.115
uA
V
V
V
V
V
uA
Latch Protection
V
Latch_
release
Ivdd(latch)
Gate Drive Output (GATE Pin)
VOL
VOH
Gate_Clamp
T_r
T_f
Io = 20 mA (sink)
Io = 20 mA (source)
VDD=24V
GATE = 1nF
GATE = 1nF
0.3
11
18
120
50
V
V
V
nSec
nSec
Note 1.
Stresses beyond those listed under
“Absolute
Maximum Ratings” may cause permanent damage to
the device. These are stress ratings only, and functional operation of the device at these or any other
conditions beyond those indicated in the operational sections of the specifications is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Note 2.
The device is not guaranteed to function outside its operating conditions.
Note 3.
The OLP debounce time is proportional to the period of switching cycle.
Note 4.
Guaranteed by design.
©SiFirst Technology
-5-
Confidential
SiFirst_DS_1560_V1.1
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