MDT10P611
-
PB5~1 Interrupt on pin change
1. General Description
This EPROM-Based 8-bit micro-controller uses a fully
static CMOS technology process to achieve higher
speed
and
smaller
size
with
the
low
power
MDT10P611P12
MDT10P611S12
consump-tion and high noise immunity. On chip memory
includes 1K words of ROM, and 64 bytes of static RAM.
PINS
14
14
I/O
12
12
OSC
IRC
8MHz/4MHz
-
PA5~0 Interrupt on pin change
-
TMR1 and PR1 Compare
3. Applications
2. Features
The followings are some of the features on the
hardware and software :
Fully CMOS static design
8-bit data bus
On chip ROM size : 1K words
Internal RAM size : 64 bytes
37 single word instructions
14-bit instructions
8-level stacks
Operating voltage : 2.5 V ~ 5.5 V
Built in 8MHz, 4MHz internal RC
Oscillator can be selected by programming
option:
INTRC－Internal 8MHz/4MHz
Addressing modes include direct, indirect and
relative
addressing modes
Power-on Reset
Power edge-detector Reset
Sleep Mode for power saving
8-bit real time clock/counter(RTCC) with 8-bit
programmable prescaler
Soft-ware I/O pull-up/down or open-drain control
On-chip RC oscillator based Watchdog
Timer(WDT)
Timer 1: 8-bit PWM/counter with 8 bit period
five interrupt source：
The application areas of this 10P611 range from
appliance motor control and high speed automotive to
low power remote transmitters/receivers, small
instruments, toy, automobile.
-
External INT Pin (PB0)
-
Timer0
This specification are subject to be changed without notice. Any latest information please preview
http://www.mdtic.com.tw
P. 1
2011/08
Ver. 1.0
MDT10P611
4. Pin Assignment
10P611P12/S12
PA2
PA1
PA0
VDD
PB5
PB4
PB3
1
2
3
4
5
6
7
14
13
12
11
10
9
8
PA3
PA4
PA5
VSS
PB0/INT
PB1
PB2/T0CI
5. Pin Function Description
Pin Name
PA5~0
I/O
I/O
Port A, TTL input level.
PA5~PA0: Interrupt on pin change. Software select PWM2 output
Software controlled pull-high (100K/5V) /pull-low (100K/5V)
/open-drain.
PB5~0
I/O
Port B, TTL input level
PB0: External INT input. PB5~PB1: Interrupt on pin change.
PB5、4、2、1 Software select PWM1 output
Software controlled pull-high (100K/5V) /pull-low (100K/5V)
/open-drain.
PB3 input only.
VDD
VSS
Power supply
Ground
Function Description
6. Memory Map
(A) Register Map
This specification are subject to be changed without notice. Any latest information please preview
http://www.mdtic.com.tw
P. 2
2011/08
Ver. 1.0
MDT10P611
Address
Bank 0
00
01
02
03
04
05
06
08
09
0A
0B
0C
0D
0E
10~4F
50
51
52
53
54
55
Bank 1
01
05
06
07
08
09
0C
0D
0E
TMR0
CPIO A
CPIO B
PSTA
PAIE
PAIF
/PHPA
/PLPA
/ODPA
Indirect Addressing Register
RTCC
PCL
STATUS
MSR
Port A
Port B
PBIE
PBIF
PCHLAT
INTS
/PHPB
/PLPB
/ODPB
64 bytes General purpose registers
TMR1
PR1
Duty cycle1
T1CON
Duty cycle2
CHSA
Description
This specification are subject to be changed without notice. Any latest information please preview
http://www.mdtic.com.tw
P. 3
2011/08
Ver. 1.0
MDT10P611
(1) IAR (Indirect Address Register): R0
(2) RTCC (Real Time Clock/Counter register): R01
(3) PC (Program Counter): R02, R0A
Write PC --- from PCHLAT
LJUMP, LCALL --- from instruction word
RTWI, RET, RTFI --- from STACK
A9
A8
A7~A0
Write PC --- from ALU
LJUMP, LCALL --- from instruction word
RTWI, RET, RTFI --- from STACK
(4) STATUS (Status register): R3
Bit
0
1
2
3
4
5
Symbol
C
HC
Z
PF
TF
RBS0
Carry bit
Half Carry bit
Zero bit
Power down bit
WDT Timer overflow Flag bit
Register Bank select bit
0: 00h~7Fh
1: 80h~FFh
General Purpose bit
Function
7~6
--
(5) MSR (Memory Bank Select Register): R4
b7
b6
b5
b4
b3
b2
b1
b0
Memory Bank Select Register
0: 00h~7Fh
1: 80h~FFh
Indirect Addressing Mode
(6) PORT A: R05
PA5~PA0, I/O register.
(7) PORT B: R06
PB5~PB0, I/O register, PB3 input only.
This specification are subject to be changed without notice. Any latest information please preview
http://www.mdtic.com.tw
P. 4
2011/08
Ver. 1.0
MDT10P611
(8) PBIE: R08
Bit
0
1
2
3
4
5
7~6
(9) PBIF: R09
Bit
0
1
2
3
4
5
7~6
(10) INTS: R0B
Bit
0
1
2
3
4
5
Symbol
--
INTF
TIF
--
INTS
TIS
Reserved, Read as “0”
Set when INT interrupt occurs INT interrupt flag.
Set when TMR0 overflows.
Reserved, Read as “0”
0: Disable INT interrupt
1: Enable INT interrupt
0: Disable TMR0 interrupt
1: Enable TMR0 interrupt
Function
Symbol
--
PB1IF
PB2IF
PB3IF
PB4IF
PB5IF
--
Reserved, Read as “0”
0: No PB1 pin change interrupt occurred
1: The PB1 pin change interrupt occurred
0: No PB2 pin change interrupt occurred
1: The PB2 pin change interrupt occurred
0: No PB3 pin change interrupt occurred
1: The PB3 pin change interrupt occurred
0: No PB4 pin change interrupt occurred
1: The PB4 pin change interrupt occurred
0: No PB5 pin change interrupt occurred
1: The PB5 pin change interrupt occurred
Reserved, Read as “0”
Function
Symbol
--
PB1IE
PB2IE
PB3IE
PB4IE
PB5IE
--
Reserved, Read as “0”
0: Disable PB1 pin change interrupt
1: Enable PB1 pin change interrupt
0: Disable PB2 pin change interrupt
1: Enable PB2 pin change interrupt
0: Disable PB3 pin change interrupt
1: Enable PB3 pin change interrupt
0: Disable PB4 pin change interrupt
1: Enable PB4 pin change interrupt
0: Disable PB5 pin change interrupt
1: Enable PB5 pin change interrupt
Reserved, Read as “0”
Function
This specification are subject to be changed without notice. Any latest information please preview
http://www.mdtic.com.tw
P. 5
2011/08
Ver. 1.0
Microchip MCU
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