MXD8530 – SP3T Switch for 0.1½3G Application
General Description
The MXD8530 is a Single Pole, Triple-Throw
(SP3T)
antenna
switch.
The
high
linearity
performance and low insertion loss achieved by
the MXD8530 make it an ideal choice for
main/diversity switching commonly used in LTE-
based handsets, data cards, and tablets that use
antenna diversity solutions. The symmetric port
designs provide flexibility in signal routing for both
receive diversity and higher power WCDMA/FDD,
and WLANs transmit/receive applications.
Switching
is
controlled
by
two
CMOS/TTL-
compatible control voltage inputs (V1 and V2).
Depending on the logic voltage level applied to the
control pins, the ANT pin is connected to one of
five switched RF outputs (RF1 to RF2) using a low
insertion loss path, while the paths between the
ANT pin and the other RF pins are in a high
isolation state. No external blocking capacitors are
required on the RF paths unless VDC is externally
applied.
The MXD8530 is manufactured in a compact, 12-
pin 2.0 x 2.0 mm, Quad Flat No-Lead (QFN)
package. A functional block diagram is shown in
Figure 1. The pin configuration and package are
shown in Figure 2. Signal pin assignments and
functional pin descriptions are provided in Table 1.
Applications
WCDMA band and mode switching
Antenna switch for multimode systems
802.11 b/g/n WLANs
Features
Broadband frequency range: 0.1 to 3.0 GHz
Low insertion loss: 0.45 dB typical @ 2.5 GHz
High isolation: >30 dB @ 2.5 GHz
No external DC blocking capacitors requires
Small QFN (12-pin, 2.0 x 2.0 mm) package
Functional Block Diagram and Pin Function
Figure 1. Functional Block Diagram
Figure 2. Pin Diagram
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Recommended Operation Range
Table 3.
Parameters
Operation Frequency
Power supply
Switch Control Voltage (H)
Switch Control Voltage (L)
Symbol
f1
VDD
V
H
V
L
Min
0.1
2.0
1.0
0
Typ
-
2.8
1.8
0
Max
3.0
3.0
3.0
0.3
Units
GHz
V
V
V
Specifications
Table 4. Electrical Specifications
Parameter
DC Specifications
Supply voltage
Supply current
Control current
Shutdown mode supply
current
VDD
IDD
ICTL
IOFF
2.0
2.8
83
2
5
3.0
V
μA
μA
μA
VCTL = 1.8 V
V1/2/3 = 1.8 V, VDD = 3 V
50% of final control
Turn-on switching time
Ton
2
μs
voltage to 90% of final RF
power, switching between
RF1/2/3
Symbol
Min.
Specification
Typical
Max.
Units
Test Condition
(Note 2)
RF Specifications
Insertion loss (RFC pin to
RF1/2/3 pins)
Isolation (RFC pin to
RF1/2/3 pins)
Input return loss (RFC pin to
RF1/2/3 pins)
Second harmonics (RFC pin
to RF1/2/3 pins)
Third harmonics (RFC pin to
RF1/2/3 pins)
0.1 dB Compression Point
(ANT pin to RF1/2/3 pins)
3
rd
Order Input Intercept
Point
IIP3
+65
+70
dBm
ISO
IL
38
29
26
RL
2fo
3fo
P
0.1dB
0.35
0.40
0.45
45
36
33
-20
+85
+85
+36
0.40
0.50
0.55
dB
dB
dB
dB
dB
dB
dB
dBc
dBc
dBm
0.8 to 1.0 GHz
1.0 to 2.2 GHz
2.2 to 3.0 GHz
0.8 to 1.0 GHz
1.0 to 2.2 GHz
2.2 to 3.0 GHz
0.8 to 3.0 GHz
PIN = +20 dBm,
0.1 to 3.0 GHz
PIN = +20 dBm,
0.1 to 3.0 GHz
0.1 GHz to 3 GHz
@ 3.0 GHz,
PIN = +20 dBm,
Δf = 1 MHz
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Absolute Maximum Ratings
Table 5. Maximum ratings
Parameters
Symbol
Minimum
Maximum
Units
Supply voltage
V
DD
+2.5
+3.0
V
Control voltage (V1 and V2)
V
CTL
-0.5
+3.0
V
RF input power (RF1 to RF3)
P
IN
+36
dBm
Operating temperature
-40
+85
℃
T
OP
Storage temperature
-55
+150
℃
T
STG
Human Body Mode
HBM
1000
V
Machine Mode
MM
100
V
Charged Device Mode
CDM
500
V
Note:
Exposure to maximum rating conditions for extended periods may reduce device reliability. There is no damage to device with
only one parameter set at the limit and all other parameters set at or below their nominal value. Exceeding any of the limits listed
here may result in permanent damage to the device
Package Outline Dimension
Figure 4. package outline dimension
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