MXD8666
SP6T Switch with MIPI for LTE Diversity
VED
APPRO
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(Maxscend) and may not be reproduced in any form without express written consent of Maxscend. No
transfer or licensing of technology is implied by this document.
Page 1 of 10
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MXD8666 – SP6T Switch with MIPI for LTE Diversity
General Description
The MXD8666 is a low loss, high isolation SP6T
switch for antenna diversity receiving.
The MXD8666 is compatible with MIPI control,
which is a key requirement for many cellular
transceivers. This part is packaged in a compact
2mm x 2mm, 14-pin, QFN package which allows for
a small solution size with no need for external DC
blocking capacitors (when no external DC is
applied to the device ports).
Features
Excellent insertion loss
- 0.50 dB Insertion Loss at 2.7GHz
P0.1dB @ 27dBm
Multi-Band operation 700MHz to 3000MHz
RFFE serial control interface
Compact 2mm x 2mm in QFN-14 package
No DC blocking capacitors required (unless
external DC is applied to the RF ports)
Applications
2G/3G/4G antenna diversity
Cellular modems and USB Devices
Functional Block Diagram and Pin Function
VDD
RF3
12
14
13
RF1
RF2
RF3
11
RF2
NC
VIO
SDATA
1
2
3
Ground
Paddle
10
9
8
RF1
ANT
GND
RF4
RF5
RF6
ANT
SCLK
4
5
6
RF5
GND
RF6
VIO
V
DD
SCLK
SDATA
Figure 1 Functional Block Diagram and Pinout (Top View)
RF4
7
Page 2 of 10
Maxscend Technologies Inc. All rights reserved.
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MXD8666 – SP6T Switch with MIPI for LTE Diversity
Application Circuit
C4
100pF
14
13
12
RF3
11
RF2
RF1
Ground
Paddle
ANT
GND
C1
33nF
C2
DN1
C3
DN1
RF1
ANT
RF6
Figure 2 MXD8666 Evaluation Board Schematic
Table 1. Pin Description
Pin No.
1
2
3
4
5
6
7
Ground
Paddle
Name
VIO
SDATA
SCLK
GND
RF6
RF5
RF4
GND
Description
Supply voltage for MIPI
MIPI data input/output
MIPI clock
Ground
RF port6
RF port5
RF port4
Ground
Pin No.
8
9
10
11
12
13
14
Name
GND
ANT
RF1
RF2
RF3
NC
VDD
Description
Ground
Antenna port
RF port1
RF port2
RF port3
NC
Power supply
Note:
Bottom ground paddles must be connected to ground.
RF5
RF4
Page 3 of 10
Maxscend Technologies Inc. All rights reserved.
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MXD8666 – SP6T Switch with MIPI for LTE Diversity
Truth Table
Table 2.
Control
Register_0
0x06
0x04
0x02
0x05
0x03
0x01
0x00
RF1
Insertion
Loss
Isolation
Isolation
Isolation
Isolation
Isolation
Isolation
RF2
Isolation
Insertion
Loss
Isolation
Isolation
Isolation
Isolation
Isolation
Switched RF Outputs
RF3
Isolation
Isolation
Insertion
Loss
Isolation
Isolation
Isolation
Isolation
RF4
Isolation
Isolation
Isolation
Insertion
Loss
Isolation
Isolation
Isolation
RF5
Isolation
Isolation
Isolation
Isolation
Insertion
Loss
Isolation
Isolation
RF6
Isolation
Isolation
Isolation
Isolation
Isolation
Insertion
Loss
Isolation
Recommended Operation Range
Table 3. Recommended Operation Condition
Parameters
Operation Frequency
Power supply
Power supply for MIPI
MIPI Control Voltage High
MIPI Control Voltage Low
Symbol
f1
V
DD
V
IO
V
H
V
L
Min
0.7
2.5
1.65
0.8*VIO
0
Typ
-
2.8
1.8
1.8
0
Max
3.0
3.0
1.95
1.95
0.3
Units
GHz
V
V
V
V
Specifications
Table 4. Electrical Specifications
Parameter
DC Specifications
Supply voltage
Supply current
V
IO
supply voltage
V
IO
Supply current
SDATA, SCLK control voltage: High
Lo
w
Switching Speed, one RF to
another
V
DD
I
DD
V
IO
I
IO
V
CTL
_
H
V
CTL
_
L
10% to 90% RF
0.8* V
IO
0
1.65
2.5
2.8
30
1.8
4
V
IO
0
1
3.0
50
1.95
10
1.95
0.3
2
V
uA
V
uA
V
V
uS
Symbol
Test Condition
Min
Typical
Max
Units
RF Specifications
Insertion loss (ANT pin to
RF1/2/3/4/5/6 pins)
Isolation (ANT pin to RF1/2/3/4/5/6
pins)
Input return loss (ANT pin to
RF1/2/3/4/5/6 pins)
0.1 dB Compression Point (ANT pin
to RF1/2/3/4/5/6 pins)
IL
0.1 to 1.0 GHz
1.0 to 2.0 GHz
2.0 to 2.7 GHz
0.1 to 1.0 GHz
1.0 to 2.0 GHz
2.0 to 2.7 GHz
0.1 to 1.0 GHz
1.0 to 2.0 GHz
2.0 to 2.7 GHz
0.7 GHz to 3.0 GHz
0.30
0.40
0.50
40
30
24
25
20
15
+27
dB
dB
dB
dB
dB
dB
dB
dB
dB
dBm
Iso
RL
P0.1dB
35
25
20
20
15
12
Page 4 of 10
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MXD8666 – SP6T Switch with MIPI for LTE Diversity
MIPI Read and Write Timing
MIPI supports the following Command Sequences:
• Register Write
• Register_0 Write
• Register Read
Figures 3 and 4 provide the timing diagrams for register write commands and read commands, respectively.
Figure 5 shows the Register 0 Write Command Sequence. Refer to the MIPI Alliance Specification for RF
Front-End Control Interface (RFFE), v1.10 (26 July 2011) for additional information on MIPI USID
programming sequences and MIPI bus specifications.
CLK
Data
SSC
SA3
SA2
SA1
SA0
0
1
0
A4
A3
A2
A1
A0
P
Register Write Command Frame
CLK
Data
P
D7
D6
D5
D4
D3
Data Frame
D2
D1
D0
P
0
Bus
Park
Signal driven by Master
Signal not driven, pull down only
For reference only
Figure 3 Register Write Command Sequence
CLK
Data
SSC
SA3
SA2
SA1
SA0
0
1
1
A4
A3
A2
A1
A0
P
Register Read Command Frame
CLK
Data
P
0
Bus
Park
D7
D6
D5
D4
D3
D2
D1
D0
P
0
Bus
Park
Data Frame (from Slave)
Signal driven by Master
Signal driven by Slave
Signal not driven, pull down only by Master
For reference only
Figure 4 Register Read Command Sequence
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