JMTL3415K
Description
JMT P-channel MOSFET
Features
V
DS
=-20V, I
D
=-4A
R
DS(ON)
=38mΩ (Typ.) @ V
GS
= -4.5V
R
DS(ON)
=48mΩ (Typ.) @ V
GS
= -2.5V
High Power and Current Handing Capability
Lead Free Product is Acquired
Surface Mount Package
ESD Rating: HBM 2.0KV
Application
PWM Applications
Load Switch
Power Management
Package
SOT-23
Absolute Maximum Ratings
(T
C
=25℃ unless otherwise specified)
Symbol
V
DSS
V
GSS
I
D
I
DM
P
D
R
θJA
T
J
, T
STG
Parameter
Drain-Source Voltage
Gate-Source Voltage
Continuous Drain Current
Pulsed Drain Current
note1
Power Dissipation
T
A
= 25℃
Thermal Resistance, Junction to Ambient
Operating and Storage Temperature Range
T
C
= 25℃
T
C
= 100℃
Max.
-20
±8
-4
-2.6
-20
1.67
75
-55 to +150
Units
V
V
A
A
W
℃/W
℃
JieJie Microelectronics CO. , Ltd
-1-
Version :C
JMTL3415K
Electrical Characteristics
(T
C
=25℃ unless otherwise specified)
Symbol
Off Characteristic
V
(BR)DSS
I
DSS
I
GSS
V
GS(th)
R
DS(on)
g
FS
C
iss
C
oss
C
rss
Q
g
Q
gs
Q
gd
t
d(on)
t
r
t
d(off)
t
f
Drain-Source Breakdown Voltage
Zero Gate Voltage Drain Current
Gate to Body Leakage Current
Gate Threshold Voltage
Static Drain-Source on-Resistance
note2
Parameter
Test Condition
Min.
Typ.
Max.
Units
V
GS
=0V,I
D
= -250μA
V
DS
= -20V, V
GS
= 0V,
V
DS
=0V, V
GS
= ±8V
V
DS
= V
GS
, I
D
= -250μA
V
GS
=-4.5V, I
D
=-4A
V
GS
=-2.5V, I
D
=-3A
V
DS
=-5V, I
D
= -4A
-20
-
-
-0.4
-
-
8
-
-
-
-
-
-
-
-
-
-
-
38
48
-
950
165
120
12
1.4
3.6
12
10
19
25
-
-1
±10
-1.0
48
65
-
-
-
-
-
-
-
-
-
-
-
V
μA
μA
V
mΩ
S
pF
pF
pF
nC
nC
nC
ns
ns
ns
ns
On Characteristics
Forward Transconductance
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Total Gate Charge
Gate-Source Charge
Gate-Drain(“Miller”) Charge
Turn-on Delay Time
Turn-on Rise Time
Turn-off Delay Time
Turn-off Fall Time
Dynamic Characteristics
V
DS
= -10V, V
GS
= 0V,
f = 1.0MHz
V
DS
= -10V, I
D
= -4A,
V
GS
= -4.5V
Switching Characteristics
V
DD
=-10V, V
GS
=-4.5A,
R
L
=2.5Ω,R
GEN
=3Ω
-
-
-
Drain-Source Diode Characteristics and Maximum Ratings
I
S
I
SM
V
SD
Maximum Continuous Drain to Source Diode Forward
Current
Maximum Pulsed Drain to Source Diode Forward Current
Drain to Source Diode Forward
Voltage
V
GS
= 0V, I
S
= -4A
-
-
-
-
-
-
-4
-20
-1.2
A
A
V
Notes:1. Repetitive Rating: Pulse Width Limited by Maximum Junction Temperature
2. Pulse Test: Pulse Width≤300μs, Duty Cycle≤2%
JieJie Microelectronics CO. , Ltd
-2-
Version :C
JMTL3415K
Typical Performance Characteristics
Figure1 :Switching Test Circuit
Figure2:Switching Waveforms
Package Mechanical Data
Dimensions
Ref.
Millimeters
Min.
A
B
C
D
E
F
G
H
0.20
0
0.10
I
2.30
2.80
0.35
1.20
0.90
Typ.
2.40
2.90
1.90 REF
0.40
1.30
1.00
0.10
0.45
1.40
1.10
0.15
0.008
0
0.004
Max.
2.50
3.00
Min.
Inches
Typ.
Max.
0.091 0.095 0.098
0.110 0.114 0.118
0.075 REF
0.014 0.016 0.018
0.047 0.051 0.055
0.035 0.039 0.043
0.004 0.006
G
H
I
A
E
C
B
D
F
SOT-23
Marking
3415
3415: Device Code
JieJie Microelectronics CO. , Ltd
-3-
Version :C
JMTL3415K
Package Information-SOT-23
D0
P0
E
P2
Ref.
Dimensions
Millimeters
3.15 ± 0.3
2.77 ± 0.3
178
1.50±0.1
1.75 ± 0.2
13.3±0.3
3.5 ± 0.2
4.00 ± 0.2
4.00 ± 0.2
2.00 ± 0.2
8.00 ± 0.2
11.5±1.0
Inches
0.124 ± 0.012
0.109 ± 0.012
7.0
0.059 ± 0.004
0.069 ± 0.008
0.524± 0.012
0.138 ± 0.008
0.157 ± 0.008
0.157 ± 0.008
0.079 ± 0.008
0.315 ± 0.008
0.453 ± 0.039
B0
W
A0
B0
C
D0
E
E1
F
P0
P1
P2
W
W1
F
A0
P1
Ordering Information-SOT-23
OUTLINE
TAPING
PACKAGE TYPE
SOT-23
QUANTITY
REEL
3,000pcs
DESCIPTION
7 inch reel pack
Information furnished in this document is believed to be accurate and reliable. However, Jiangsu
JieJie Microelectronics Co.,Ltd assumes no responsibility for the consequences of use without
consideration for such information nor use beyond it.
Information mentioned in this document is subject to change without notice, apart from that when
an agreement is signed, Jiangsu JieJie complies with the agreement.
Products and information provided in this document have no infringement of patents. Jiangsu
JieJie assumes no responsibility for any infringement of other rights of third parties which may
result from the use of such products and information.
This document is the third version which is made in 25-July-2018. This document supersedes
and replaces all information previously supplied.
is a registered trademark of Jiangsu JieJie Microelectronics Co.,Ltd.
Copyright ©2018 Jiangsu JieJie Microelectronics Co.,Ltd. Printed All rights reserved.
JieJie Microelectronics CO. , Ltd
-4-
Version :C
FPGA/CPLD
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