HYM1380/1381
Serial Real Time Clock/Calendar
Features
■
Provides year, month, day, weekday, hours,
minutes and seconds based on 32.768 kHz
quartz crystal
■
Serial I/O transmission: Simple 3–wire interface
■
Clock registers store BCD format
■
2.0–5.5 volt full operation
■
Uses less than 400nA at 2.0 volts
■
Single–byte or multiple–byte (burst mode) data
transfer for read or write of clock
■
8–pin DIP for HYM1380, 8–pin SOP package for
HYM1381
■
Maximum input serial clock: 500kHz at V
CC
=2V，
2MHz at V
CC
=5V
■
TTL–compatible (V
DD
= 5V)
Applications
■
Cash Register
■
Security Access Controller, Door Controller
■
Time Recorder
■
Mobile Telephones
■
Public Phone Bill Meter, Smart Card Payphone
■
IC Water-Flow Meter, IC Gas Meter
General Description
The
HYM1380/HYM1381
is a serial timekeeper IC which provides seconds, minutes, hours, day, date,
month, and year information. It communicates with a microprocessor via a simple serial interface. The end of
the month date is automatically adjusted for months with less than 31 days, including corrections for leap year.
The clock operates in either the 24–hour or 12–hour format with an AM/PM indicator.
Interfacing the
HYM1380/HYM1381
with a microprocessor is simplified by using synchronous serial
communication. Only three wires are required to communicate with the clock: (1)
RST
(Reset), (2) I/O (Data
line), and (3) SCLK (Serial clock). Data can be transferred to and from the clock 1 byte at a time or in a burst
mode. The
HYM1380/HYM1381
is designed to operate on very low power.
Ordering Information
Part
HYM1380
HYM1381
Temp Range
0°C to +70°C
0°C to +70°C
Pin-Package
8 DIP
8 SOP
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1380/1381
Block Diagram and Pin Description
Block Diagram
X1
Divider
X2
Vcc
+ 5V
Da ta b us
Minute
Hour
Day
Week
Month
Y
ear
ROM
Ad d re ss b u s
command
decoder
Shift
Register
I/O
SCLK
RST
GND
Pin Assignment
HYM1380 —8DIP, HYM1381 —8SOP
Pin Description
Pin No.
1
2
3
4
5
6
7
8
Symbol
NC
X1
X2
GND
RST
Description
No Connection
Connections for a standard 32.768kHz quartz crystal
Connections for a standard 32.768kHz quartz crystal
Ground
The reset signal must be asserted high during a read or a write,
The I/O pin is the bi-directional data pin for the 3-wire interface
The SCLK pin is used to synchronize data movement on the serial interface
Power Supply Pin
I/O
SCLK
V
CC
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-2-
1380/1381
Absolute Maximum Rating
Parameter
Supply Voltage
Operating Temperature
Storage Temperature
Soldering Temperature
Symbol
Value
Unit
V
CC
T
A
T
S
T
H
－0.3½5.5
0½70
-50½+125
260（10 Sec）
V
℃
℃
℃
Note:
These stress ratings only. Stress exceeding the range specified under "Absolute Maximum Ratings" may cause
substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the
specification. not implied and prolonged to extreme conditions may affect device reliability.
Electrical Characteristics
DC Electrical Characteristics
(T
A
=25℃,
V
CC
= 2.0 to 5.5V
,
Unless otherwise noted.
)
Parameter
Symbol
Test Condition
V
DD
－
2V
5V
2V
5V
5V
5V
5V
2V
5V
Condition
Min
Typical
Max
Unit
Supply Voltage
Standby Current
Operating Current
Logic 1 Intput
Logic 0 Intput
V
cc
I
STB
I
cc
V
IH
V
IL
fosc
f
SCLK
－
－
No Load
－
－
32.768KHz
－
2
－
－
－
－
－
0.7
0.7
5.5
100
100
1.0
1.2
－
0.8
－
0.5
2
V
nA
nA
μA
μA
V
V
KHz
MHz
MHz
2
－
－
－
－
－
－
32.768
－
－
System
Frequency
CLK Frequency
AC Electrical Characteristics
(T
A
=25℃,
V
CC
= 2.0 to 5.5V
,
Unless otherwise noted.
)
Parameter
CLK to
RST
Hold
RST
Inactive Time
RST
to I/O High Z
Symbol
t
cch
t
cwh
t
cdz
t
ccz
t
dc
t
cdh
t
cdd
Test Condition
V
CC
=2.0V
V
CC
=5V
V
CC
=2.0V
V
CC
=5V
V
CC
=2.0V
V
CC
=5V
V
CC
=2.0V
V
CC
=5V
V
CC
=2.0V
V
CC
=5V
V
CC
=2.0V
V
CC
=5V
V
CC
=2.0V
Min
240
60
4
1
Max
Unit
ns
ns
280
70
280
70
200
50
280
70
800
ns
ns
ns
ns
ns
-3-
SCLK to I/O High Z
Data to CLK Setup
CLK to Data Hold
CLK to Data Delay
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1380/1381
V
CC
=5V
CLK Low Time
CLK High Time
CLK Frequency
CLK Rise and Fall
RST
to CLK Setup
200
1000
250
1000
250
0.5
DC
2.0
2000
500
4
1
ns
ns
MHz
ns
µs
t
cl
t
ch
t
clk
t
r
，t
f
t
CC
V
CC
=2.0V
V
CC
=5V
V
CC
=2.0V
V
CC
=5V
V
CC
=2.0V
V
CC
=5V
V
CC
=2.0V
V
CC
=5V
V
CC
=2.0V
V
CC
=5V
Timing Diagram: Read Data Transfer
Timing Diagram: Write Data Transfer
Application Information
Command Byte
For each data transfer, a command byte is initiated to specify which register is accessed. This is to determine
whether a read or write is operated and whether a single byte or burst mode transfer is to occur. The
command byte is shown in Table 1.
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-4-
1380/1381
Table 1 Address/ Command Byte
1
0
0
0
A2
A1
A0
R/W
The MSB (Bit 7) must be logic 1. If it is 0, writes to the HYM1380/1381 will be disabled. A2-A0 (Bits 1 through
3) specify the designated registers to be input or output, and the R/W (bit 0) specifies a write operation if logic
0 or read operation if logic 1. The command byte is always input starting with the LSB (bit 0).
Clock/Calendar
The clock/calendar is contained in seven write/read registers. Data contained in the clock/ calendar registers
is in binary coded decimal format (BCD). The registers and data format summary is shown in Table 2.
Table 2 Registers Address/Definition
Register
Name
Seconds
Minutes
Hours
Date
Month
Day
Year
Control
Range
Data
00-59
00-59
01-12
00-23
01-31
01-12
01-07
00-99
D7
CH
0
12/
24
0
0
0
WP
D6
10SEC
10MIN
0
0
0
0
0
0
AP
10
0
0
0
HR
HR
DATE
MONTH
DAY
YEAR
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
1
1
1
0
1
0
1
1/0
1/0
1/0
1/0
1/0
10M
0
Register Definition
D5
D4
D3
MIN
HOUR
D2
SEC
D1
D0
1
1
1
1
0
0
0
0
The command byte
0
0
0
0
0
0
0
0
A2
0
0
0
A1
0
0
1
A0
0
1
0
R/W
1/0
1/0
1/0
10DATE
10 YEAR
Data Transfer
To initiate any transfer of data,
RST
is taken high and the command word is loaded into the shift register
providing both address and command information. Data is serially input on the rising edge of the SCLK. The
first 8 bits specify which of 8 bytes will be accessed, whether a read or write cycle will take place, and whether
a byte or burst mode transfer is to occur. After the first eight clock cycles have loaded the command word into
the shift register, additional clocks will output data for a read or input data for a write. All data is serially input
on the rising edge of SCLK and outputs on the falling edge of SCLK. The data transfer summary is shown in
Figure 1.
Wuhan Haoyu Microelectronic Co.,ltd. Tel:+86 -27-8266-6619 Fax:+86 -27-5971-6818 Http:www.haoyu-ic.com
-5-
PCB设计
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