Fremont Micro Devices
FT24C32A-Exx
Two-Wire Serial EEPROM
32K (8-bit wide)
FEATURES
Low voltage and low power operations:
FT24C32A:
V
CC
= 1.8V to 5.5V
32 bytes page write mode.
Partial page write operation allowed.
Internally organized: 4,096
×
8 (32K).
Standard 2-wire bi-directional serial interface.
Schmitt trigger, filtered inputs for noise protection.
Self-timed Write Cycle (5ms maximum).
1000 kHz (2.5V-5V), 400 kHz (1.8V) Compatibility.
Automatic erase before write operation.
Write protect pin for hardware data protection.
High reliability: typically 1,000,000 cycles endurance.
100 years data retention.
Industrial temperature range (-40℃ to 85℃).
Standard 8-lead DIP/SOP/MSOP/TSSOP/DFN and 5-lead SOT23/TSOT23 Pb-free packages.
DESCRIPTION
The FT24C32A series are 32,768 bits of serial Electrical Erasable and Programmable Read Only Memory,
commonly known as EEPROM. They are organized as 4096 words of 8 bits (one byte) each. The devices
are fabricated with proprietary advanced CMOS process for low power and low voltage applications.
These devices are available in standard 8-lead DIP, 8-lead SOP, 8-lead MSOP, 8-lead TSSOP, 8-lead
DFN, 5-lead SOT23, and 5-lead TSOT23 packages. A standard 2-wire serial interface is used to address
all read and write functions. Our extended V
CC
range (1.8V to 5.5V) devices enables wide spectrum of
applications.
PIN CONFIGURATION
Pin Name
A2, A1, A0
SDA
SCL
WP
NC
VCC
GND
Pin Function
Device Address Inputs
Serial Data Input / Open Drain Output
Serial Clock Input
Write Protect
No-Connect
Power Supply
Ground
© 2019 Fremont Micro Devices Inc.
Confidential Rev1.4
DS24C32A-Exx--page1
Fremont Micro Devices
All these packaging types come in Pb-free certified.
FT24C32A-Exx
ABSOLUTE MAXIMUM RATINGS
Industrial operating temperature:
Storage temperature:
Input voltage on any pin relative to ground:
Maximum voltage:
ESD Protection on all pins:
-40℃ to 85℃
-50℃ to 125℃
-0.3V to V
CC
+ 0.3V
8V
>2000V
* Stresses exceed those listed under “Absolute Maximum Rating” may cause permanent damage to the
device. Functional operation of the device at conditions beyond those listed in the specification is not
guaranteed. Prolonged exposure to extreme conditions may affect device reliability or functionality.
PIN DESCRIPTIONS
© 2019 Fremont Micro Devices Inc.
Confidential Rev1.4
DS24C32A-Exx--page2
Fremont Micro Devices
(A) SERIAL CLOCK (SCL)
FT24C32A-Exx
The rising edge of this SCL input is to latch data into the EEPROM device while the falling edge of this
clock is to clock data out of the EEPROM device.
(B) DEVICE / CHIP SELECT ADDRESSES (A2, A1, A0)
These are the chip select input signals for the serial EEPROM devices. Typically, these signals are
hardwired to either V
IH
or V
IL
. If left unconnected, they are internally recognized as V
IL
. However, due to
capacitive coupling that may appear in customer applications, FMD recommends always connecting the
address pins to a known state. When using a pull-up or pull-down resistor, FMD recommends using
10kΩ or less.
(C) SERIAL DATA LINE (SDA)
SDA data line is a bi-directional signal for the serial devices. It is an open drain output signal and can be
wired-OR with other open-drain output devices.
(D) WRITE PROTECT (WP)
The FT24C32A devices have a WP pin to protect the whole EEPROM array from programming.
Programming operations are allowed if WP pin is left un-connected or input to V
IL
.
Conversely all
programming functions are disabled if WP pin is connected to V
IH
or V
CC
. Read operations is not affected
by the WP pin’s input level. If left unconnected, it is internally recognized as V
IL
. However, due to
capacitive coupling that may appear in customer applications, FMD recommends always connecting the
WP pin to a known state. When using a pull-up or pull-down resistor, FMD recommends using 10kΩ or
less.
MEMORY ORGANIZATION
The FT24C32A devices have 128 pages respectively. Since each page has 32 bytes, random word
addressing to FT24C32A will require 12 bits data word addresses respectively.
DEVICE OPERATION
(A) SERIAL CLOCK AND DATA TRANSITIONS
The SDA pin is typically pulled to high by an external resistor. Data is allowed to change only when
Serial clock SCL is at VIL.
condition as described below.
(B) START CONDITION
With SCL
VIH, a SDA transition from high to low is interpreted as a START condition. All valid
commands must begin with a START condition.
(C) STOP CONDITION
Any SDA signal transition may interpret as either a START or STOP
© 2019 Fremont Micro Devices Inc.
Confidential Rev1.4
DS24C32A-Exx--page3
Fremont Micro Devices
With SCL
FT24C32A-Exx
VIH, a SDA transition from low to high is interpreted as a STOP condition. All valid read or
A STOP condition after page or byte write command will trigger the chip into the
write commands end with a STOP condition. The device goes into the STANDBY mode if it is after a
read command.
(D) ACKNOWLEDGE
The 2-wire protocol transmits address and data to and from the EEPROM in 8 bit words. The EEPROM
acknowledges the data or address by outputting a "0" after receiving each word. The ACKNOWLEDGE
signal occurs on the 9th serial clock after each word.
STANDBY mode after the self-timed internal programming finish (see Figure 1).
(E) STANDBY MODE
The EEPROM goes into low power STANDBY mode after a fresh power up, after receiving a STOP bit
in read mode, or after completing a self-time internal programming operation.
(F) SOFT RESET
After an interruption in protocol power loss or system reset, any two-wire part can be reset by following these
steps:
1. Creat a START condition,
2. Clock eighteen data bits “1”,
3. Creat a start condition as SDA is high.
Figure 1: Timing diagram for START and STOP conditions
SCL
SDA
START
Condition
Data
Valid
Data
Transition
STOP
Condition
Figure 2: Timing diagram for output ACKNOWLEDGE
© 2019 Fremont Micro Devices Inc.
Confidential Rev1.4
DS24C32A-Exx--page4
Fremont Micro Devices
FT24C32A-Exx
START Condition
SCL
Data in
Data out
ACK
DEVICE ADDRESSING
The 2-wire serial bus protocol mandates an 8 bits device address word after a START bit condition to invoke
a valid read or write command. The first four most significant bits of the device address must be 1010,
which is common to all serial EEPROM devices. The next three bits are device address bits. These three
device address bits (5th, 6th and 7th) are to match with the external chip select/address pin states. If a
match is made, the EEPROM device outputs an ACKNOWLEDGE signal after the 8th read/write bit,
otherwise the chip will go into STANDBY mode. However, matching may not be needed for some or all
device address bits (5th, 6th and 7th) as noted below. The last or 8th bit is a read/write command bit. If the
8th bit is at VIH then the chip goes into read mode. If a “0” is detected, the device enters programming
mode.
WRITE OPERATIONS
(A) BYTE WRITE
A write operation requires two 8-bit data word address following the device address word and
ACKNOWLEDGE signal. Upon receipt of this address, the EEPROM will respond with a “0” and then
clock in the first 8-bit data word. Following receipt of the 8-bit data word, the EEPROM will again output
a “0”. The addressing device, such as a microcontroller, must terminate the write sequence with a
STOP condition. At this time the EEPROM enters into an internally-timed write cycle state. All inputs
are disabled during this write cycle and the EEPROM will not respond until the writing is completed
(figure 3).
(B) PAGE WRITE
The 32K EEPROM are capable of 32-byte page write.
A page write is initiated the same way as a byte write, but the microcontroller does not send a STOP
condition after the first data word is clocked in. The microcontroller can transmit up to 31 more data
words after the EEPROM acknowledges receipt of the first data word. The EEPROM will respond with a
“0” after each data word is received. The microcontroller must terminate the page write sequence with a
STOP condition (see Figure 4).
The lower five bits of the data word address are internally incremented following the receipt of each data
word. The higher data word address bits are not incremented, retaining the memory page row location.
© 2019 Fremont Micro Devices Inc.
Confidential Rev1.4
DS24C32A-Exx--page5
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