Fremont Micro Devices
Preliminary 93C46/A, 56/A, 66/A
3-Wire Serial EEPROM
1K, 2K and 4Kbit (8-bit or 16-bit wide)
FEATURES
Industrial Temperature Range (-40
o
C to 85
o
C).
Standard 8-pin DIP/SOP/TSSOP/DFN Pb-free Packages.
DESCRIPTION
The FT93C46/56/66 series are 1024/2048/4096 bits of serial Electrical Erasable and Programmable
Read Only Memory, commonly known as EEPROM. They are organized as 64/128/256 words of 16 bits
each when the ORG pin is connected to VCC (or unconnected) and 128/256/512 words of 8 bits (1 byte)
each when the ORG pin is tied to ground. The devices are fabricated with proprietary advanced CMOS
process for low power and low voltage applications. These devices are available in standard 8-lead DIP,
8-lead JEDEC SOP, 8-lead TSSOP and 8-lead DFN packages. Our extended V
CC
range (1.8V to 5.5V)
devices enables wide spectrum of applications.
The FT93C46/56/66 is enabled through the Chip Select pin (CS), and accessed via a 3-wire serial
interface consisting of Data Input (DI), Data Output (DO), and Shift Clock (SCL). Upon receiving a READ
instruction at DI, the address is decoded and the data is clocked out serially on the data output pin DO.
The WRITE cycle is completely self-timed and no separate ERASE cycle is required before WRITE. The
WRITE cycle is only enabled when the part is in the ERASE/WRITE ENABLE state. Once a device
begins its self-timed program procedure, the data out pin (DO) can indicate the READY/BUSY status by
rising chip select (CS).
FM
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FT93C66: 512 x 8 or 256 x 16
2 MHz Clock Rate (5V) Compatibility.
Industry Standard 3-wire Serial Interface.
Self-Timed ERASE/WRITE Cycles (5ms max including auto-erase).
Automatic ERAL before WRAL.
Sequential READ Function.
High Reliability: Typical 1 Million Erase/Write Cycle Endurance.
100 Years Data Retention.
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Standard Voltage and Low Voltage Operation:
FT93C46/56/66:
V
CC
= 2.5V to 5.5V
FT93C46A/56A/66A:
V
CC
= 1.8V to 5.5V
User Selectable Internal Organization:
FT93C46: 128 x 8 or 64 x 16
FT93C56: 256 x 8 or 128 x 16
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Fremont Micro Devices
Preliminary 93C46/A, 56/A, 66/A
PIN CONFIGURATION
Pin Name
CS
SCL
DI
DO
ORG
DC
VCC
GND
Pin Function
Chip Select
Serial Clock
Serial Data Input
Serial Data Output
Internal Organization
Don’t Connect
Power Supply
Ground
All these packaging types come in Pb-free certified.
2
3
4
7
6
5
on
8L
8L
8L
8L
DIP
SOP
TSSOP
DFN
ABSOLUTE MAXIMUM RATINGS
Industrial operating temperature:
Storage temperature:
Input voltage on any pin relative to ground:
Maximum voltage:
FM
* Stresses exceed those listed under “Absolute Maximum Rating” may cause permanent damage
to the device. Functional operation of the device at conditions beyond those listed in the
specification is not guaranteed. Prolonged exposure to extreme conditions may affect device
reliability or functionality.
© 2013 Fremont Micro Devices Inc.
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-40
o
C to 85
o
C
-50
o
C to 125
o
C
-0.3V to V
CC
+ 0.3V
8V
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DC
VCC
CS
SCL
1
2
3
4
8
7
6
5
CS
SCL
DI
DO
1
8
VCC
DC
ORG
GND
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ORG
GND
DO
DI
8L SOP
Rotated (R)
93C46 only
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Fremont Micro Devices
93C46/A, 93C56/A, 93C66/A
PIN DESCRIPTIONS
(A) SERIAL CLOCK (SCL)
The rising edge of this SCL input is to latch data into the EEPROM device while the rising edge of this
clock is to clock data out of the EEPROM device.
This is the chip select input signal for the serial EEPROM device.
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(B) CHIP SELECT (CS)
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DS93CXX-A-page3
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(C) SERIAL DATA INPUT (DI)
This is data input signal for the serial device.
(D) SERIAL DATA OUTPUT (DO)
This is data output signal for the serial device.
(E) INTERNAL ORGANIZATION (ORG)
This is internal organization input signal for the serial EEPROM device. When the ORG pin is
connected to VCC or unconnected the EEPROM is organized as 64/128/256 word of 16 bits each and
when ORG pin is connected to ground the EEPROM is organized as 128/256/512 byte of 8 bits each.
Typically, these signals are hardwired to either V
IH
or V
IL
. If left unconnected, they are internally
recognized as V
IH
.
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Fremont Micro Devices
Preliminary 93C46/A, 56/A, 66/A
MEMORY ORGANIZATION
The FT93C46/56/66 memory is organized either as bytes (x8) or as words (x16). If Internal Organization
(ORG) is unconnected (or connected to VCC) the words (x16) organization is selected; When Internal
Organization is connected to ground the bytes (x8) organization is selected.
INSTRUCTION SET for the FT93C46
Instruction
READ
EWEN
EWDS
ERASE
WRITE
ERAL
WRAL
SB
1
1
1
1
1
1
1
Op
Code
10
00
00
11
01
00
00
Address
x8
x 16
A
6
- A
0
11xxxxx
00xxxxx
A
6
- A
0
A
6
- A
0
10xxxxx
01xxxxx
A
5
- A
0
11xxxx
00xxxx
A
5
- A
0
A
5
- A
0
10xxxx
01xxxx
D
7
- D
0
D
7
- D
0
Data
x8
x 16
Comments
Reads data stored in memory,
at specified address.
Write enable must precede all
programming modes.
Disables
all
programming
instructions.
Erase memory location A
n
- A
0
.
Writes memory location A
n
- A
0
.
Erases all memory locations.
Writes all memory locations.
D
15
- D
0
D
15
- D
0
Instruction
READ
EWEN
EWDS
ERASE
WRITE
ERAL
WRAL
.
SB
1
1
1
1
1
1
1
Op
Code
10
00
00
11
01
00
00
Address
x8
A
8
- A
0
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Data
x 16
x8
x 16
A
7
- A
0
D
7
- D
0
D
7
- D
0
D
15
- D
0
D
15
- D
0
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INSTRUCTION SET for the FT93C56 and FT93C66
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11xxxxxxx
00xxxxxxx
A
8
- A
0
A
8
- A
0
10xxxxxxx
01xxxxxxx
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(A) START BIT (SB)
Each instruction is preceded by a rising edge on Chip Select (CS) with Serial Clock (SCL) being held
Low.
(B) OPERATION CODE (OP-CODE)
Two op-code bits, read on Serial Data Input (DI) during the rising edge of Serial Clock (SCL).
(C) ADDRESS
The address bits of the byte or word that is to be accessed. For the FT93C46, the address is made
up of 6 bits for the x16 organization or 7 bits for x8 organization. For the FT93C56, the address is
made up of 7 bits for the x16 organization or 8 bits for x8 organization. For the FT93C66, the address
is made up of 8 bits for the x16 organization or 9 bits for x8 organization.
(D) DATA
The data bits of the byte or word that is to be accessed. For the FT93C46/56/66, the data is made up
of 16 bits (word) for the x16 organization or 8 bits (byte) for x8 organization.
© 2013 Fremont Micro Devices Inc.
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11xxxxxx
00xxxxxx
A
7
- A
0
A
7
- A
0
10xxxxxx
01xxxxxx
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Reads data stored in memory,
at specified address.
Write enable must precede all
programming modes.
Disables
all
programming
instructions.
Erase memory location A
n
- A
0
.
Writes memory location A
n
- A
0
.
Erases all memory locations.
Writes all memory locations.
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Fremont Micro Devices
93C46/A, 93C56/A, 93C66/A
INSTRUCTION SETS DESCRIPTION
(A) READ
The Read (READ) instruction contains the Address code for the memory location to be read. After the
instruction and address are decoded, data from the selected memory location is available at the serial
output pin DO. Output data changes are synchronized with the rising edges of serial clock SK. It
should be noted that when a dummy bit (logic “0”) precedes the 8- or 16-bit data output string.
(B) ERASE/WRITE ENABLE
To assure data integrity, the part automatically goes into the Erase/Write Disable (EWDS) state when
power is first applied. An Erase/Write Enable (EWEN) instruction must be executed first before any
programming instructions can be carried out. Please note that once in the Erase/Write Enable state,
programming remains enabled until an Erase/Write Disable (EWDS) instruction is executed or V
CC
power is removed from the part.
(C) ERASE/WRITE DISABLE
(D) ERASE
(E) WRITE
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(F) ERASE ALL
The Erase All (ERAL) instruction programs every bit in the memory array to the logic “1” state and is
primarily used for testing purposes. The DO pin outputs the READY/BUSY status of the part if CS is
brought high after being kept low for a minimum of 250 ns (t
CS
). The ERAL instruction is valid only at
V
CC
= 5.0V ± 10%.
(G) WRITE ALL
The Write All (WRAL) instruction programs all memory locations with the data patterns specified in the
instruction. The DO pin outputs the READY/BUSY status of the part if CS is brought high after being
kept low for a minimum of 250 ns (t
CS
). The WRAL instruction is valid only at V
CC
= 5.0V ± 10%.
© 2013 Fremont Micro Devices Inc.
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The Write (WRITE) instruction contains the 8 or 16 bits of data to be written into the specified memory
location. The self-timed programming cycle, t
WP
, starts after the last bit of data is received at serial
data input pin DI. The DO pin outputs the READY/BUSY status of the part if CS is brought high after
being kept low for a minimum of 250 ns (t
CS
). A logic “0” at DO indicates that programming is still in
progress. A logic “1” indicates that the memory location at the specified address has been written with
the data pattern contained in the instruction and the part is ready for further instructions. A
READY/BUSY status cannot be obtained if the CS is brought high after the end of the self-timed
programming cycle, t
WP
.
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The Erase (ERASE) instruction programs all bits in the specified memory location to the logical “1”
state. The self-timed erase cycle starts once the ERASE instruction and address are decoded. The
DO pin outputs the READY/BUSY status of the part if CS is brought high after being kept low for a
minimum of 250 ns (t
CS
). A logic “1” at pin DO indicates that the selected memory location has been
erased, and the part is ready for another instruction.
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To protect against accidental data disturb, the Erase/Write Disable (EWDS) instruction disables all
programming modes and should be executed after all programming operations. The operation of the
READ instruction is independent of both the EWEN and EWDS instructions and can be executed at
any time.
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