Fremont Micro Devices
24C512A
Two-Wire Serial EEPROM
512K (8-bit wide)
FEATURES
DESCRIPTION
The FT24C512A series are 524,288 bits of serial Electrical Erasable and Programmable Read Only
The devices are fabricated with proprietary advanced CMOS process for low power and low voltage
applications. These devices are available in standard 8-lead DIP, 8-lead SOP, 8-lead MSOP, 8-lead TSSOP
and 8-lead UDFN packages. A standard 2-wire serial interface is used to address all read and write
FM
NC
PIN CONFIGURATION
D
Pin Name
A2, A1, A0
SDA
SCL
WP
functions. Our extended VCC range (1.8V to 5.5V) devices enables wide spectrum of applications.
C
Memory, commonly known as EEPROM. They are organized as 65,536 words of 8 bits (one byte) each.
© 2016 Fremont Micro Devices Inc.
on
Device Address Inputs
Serial Clock Input
Write Protect
No-Connect
Table 1
Serial Data Input / Open Drain Output
fid
en
tia
l
Pin Function
DS24C512-A1--page1
Low voltage and low power operations:
FT24C512A:
V
CC
= 1.8V to 5.5V
Maximum Standby current < 1µA .
128 bytes page write mode.
Partial page write operation allowed.
Internally organized: 65,536×8 (512K).
Standard 2-wire bi-directional serial interface.
Schmitt trigger, filtered inputs for noise protection.
Self-timed write cycle (5ms maximum).
1 MHz (2.5-5V), 400 kHz (1.8V) compatibility.
Automatic erase before write operation.
Write protect pin for hardware data protection.
High reliability: typically 1,000,000 cycles endurance.
100 years data retention.
o
o
Industrial temperature range (-40 C to 85 C).
Standard 8-pin DIP/SOP/MSOP/TSSOP/UDFN Pb-free packages.
Fremont Micro Devices
All three packaging types come in Pb-free certified.
24C512A
FT24C512A
A0
A1
A2
GND
1
2
3
4
8
7
6
5
VCC
WP
SCL
SDA
Figure 1: Package Type
ABSOLUTE MAXIMUM RATINGS
Industrial operating temperature:
Storage temperature:
Input voltage on any pin relative to ground:
Maximum voltage:
ESD Protection on all pins:
FM
© 2016 Fremont Micro Devices Inc.
D
C
DS24C512-A1--page2
on
* Stresses exceed those listed under “Absolute Maximum Rating” may cause permanent damage to the device.
Functional operation of the device at conditions beyond those listed in the specification is not guaranteed.
Prolonged exposure to extreme conditions may affect device reliability or functionality.
fid
en
tia
l
-40 C to 85 C
o
o
-50 C to 125 C
8V
o
o
8L
8L
8L
8L
8L
DIP
SOP
MSOP
TSSOP
UDFN
-0.3V to V
CC
+ 0.3V
>2000V
Fremont Micro Devices
Figure 2: Block Diagram
24C512A
PIN DESCRIPTIONS
(A) SERIAL CLOCK (SCL)
The rising edge of this SCL input is to latch data into the EEPROM device while the falling edge of
this clock is to clock data out of the EEPROM device.
(B) DEVICE / CHIP SELECT ADDRESSES (A2, A1, A0)
hardwired to either V
IH
or V
IL
. If left unconnected, they are internally recognized as V
IL
.
(C) SERIAL DATA LINE (SDA)
SDA data line is a bi-directional signal for the serial devices. It is an open drain output signal and can
be wired-OR with other open-drain output devices.
(D) WRITE PROTECT (WP)
The FT24C512A device has a WP pin to protect the whole EEPROM array from programming.
Programming operations are allowed if WP pin is left un-connected or input to V
IL
. Conversely all
programming functions are disabled if WP pin is connected to V
IH
or V
CC
. Read operations is not
affected by the WP pin’s input level.
MEMORY ORGANIZATION
addressing to FT24C512A will require 16 bits data word addresses.
(A) SERIAL CLOCK AND DATA TRANSITIONS
FM
The SDA pin is typically pulled to high by an external resistor. Data is allowed to change only when
Serial clock SCL is at V
IL
. Any SDA signal transition may interpret as either a START or STOP
condition as described below.
(B) START CONDITION
With SCL
≥V
IH
, a SDA transition from high to low is interpreted as a START condition. All valid
commands must begin with a START condition.
(C) STOP CONDITION
With SCL
≥
V
IH
, a SDA transition from low to high is interpreted as a STOP condition. All valid read
or write commands end with a STOP condition. The device goes into the STANDBY mode if it is after
a read command. A STOP condition after page or byte write command will trigger the chip into the
© 2016 Fremont Micro Devices Inc.
DS24C512-A1--page3
D
DEVICE OPERATION
C
The FT24C512A devices have 512 pages respectively. Since each page has 128 bytes, random word
on
fid
en
tia
l
These are the chip select input signals for the serial EEPROM devices. Typically, these signals are
Fremont Micro Devices
STANDBY mode after the self-timed internal programming finish (see Figure 3).
(D) ACKNOWLEDGE
24C512A
The 2-wire protocol transmits address and data to and from the EEPROM in 8 bit words. The
EEPROM acknowledges the data or address by outputting a "0" after receiving each word. The
ACKNOWLEDGE signal occurs on the 9th serial clock after each word.
(E) STANDBY MODE
The EEPROM goes into low power STANDBY mode after a fresh power up, after receiving a STOP
SCL
SDA
START
Condition
Data
Valid
Figure 3: Timing diagram for START and STOP conditions
START Condition
SCL
FM
Data in
Data out
D
ACK
Figure 4: Timing diagram for output ACKNOWLEDGE
© 2016 Fremont Micro Devices Inc.
C
DS24C512-A1--page4
on
fid
en
tia
l
Data
Transition
STOP
Condition
bit in read mode, or after completing a self-time internal programming operation.
Fremont Micro Devices
24C512A
DEVICE ADDRESSING
The 2-wire serial bus protocol mandates an 8 bits device address word after a START bit condition to
invoke a valid read or write command. The first four most significant bits of the device address must be
1010, which is common to all serial EEPROM devices. The next three bits are device address bits. These
three device address bits (5 , 6 and 7 ) are to match with the external chip select/address pin states. If a
match is made, the EEPROM device outputs an ACKNOWLEDGE signal after the 8
th
th
th
th
th
th
th
read/write bit,
otherwise the chip will go into STANDBY mode. However, matching may not be needed for some or all
device address bits (5 , 6 and 7 ) as noted below. The last or 8th bit is a read/write command bit. If the
8 bit is at VIH then the chip goes into read mode. If a “0” is detected, the device enters programming
th
WRITE OPERATION
(A)
BYTE WRITE
A write operation requires two 8-bit data word address following the device address word and
ACKNOWLEDGE signal. Upon receipt of this address, the EEPROM will respond with a “0” and then
clock in the first 8-bit data word. Following receipt of the 8-bit data word, the EEPROM will again
output a “0”. The addressing device, such as a microcontroller, must terminate the write sequence
with a STOP condition. At this time the EEPROM enters into an internally-timed write cycle state. All
inputs are disabled during this write cycle and the EEPROM will not respond until the writing is
(B)
PAGE WRITE
The 512K EEPROM are capable of 128-byte page write.
A page write is initiated the same way as a byte write, but the microcontroller does not send a STOP
condition after the first data word is clocked in. The microcontroller can transmit up to 127 more data
with a “0” after each data word is received. The microcontroller must terminate the page write
sequence with a STOP condition (see Figure 6).
words after the EEPROM acknowledges receipt of the first data word. The EEPROM will respond
FM
word.
(C)
at the 9
th
The lower 7 bits of the data word address are internally incremented following the receipt of each data
The higher data word address bits are not incremented, retaining the memory page row
location. If more than 128 data words are transmitted to the EEPROM, the data word address will
“roll over” and the previous data will be overwritten.
ACKNOWLEDGE POLLING
ACKNOWLEDGE polling may be used to poll the programming status during a self-timed internal
programming. By issuing a valid read or write address command, the EEPROM will not acknowledge
clock cycle if the device is still in the self-timed programming mode.
th
D
C
on
completed (figure 5).
programming completes and the chip has returned to the STANDBY mode, the device will return a
valid ACKNOWLEDGE signal at the 9 clock cycle.
© 2016 Fremont Micro Devices Inc.
fid
en
tia
l
mode.
However, if the
DS24C512-A1--page5
stm32/stm8
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
